core/stdarch/crates/core_arch/src/x86_64/
avx512f.rs

1use crate::{
2    core_arch::{simd::*, x86::*, x86_64::*},
3    mem::transmute,
4};
5
6#[cfg(test)]
7use stdarch_test::assert_instr;
8
9/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer, and store the result in dst.
10///
11/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsd_i64&expand=1792)
12#[inline]
13#[target_feature(enable = "avx512f")]
14#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
15#[cfg_attr(test, assert_instr(vcvtsd2si))]
16pub fn _mm_cvtsd_i64(a: __m128d) -> i64 {
17    _mm_cvtsd_si64(a)
18}
19
20/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer, and store the result in dst.
21///
22/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtss_i64&expand=1894)
23#[inline]
24#[target_feature(enable = "avx512f")]
25#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
26#[cfg_attr(test, assert_instr(vcvtss2si))]
27pub fn _mm_cvtss_i64(a: __m128) -> i64 {
28    _mm_cvtss_si64(a)
29}
30
31/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.
32///
33/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtss_u64&expand=1902)
34#[inline]
35#[target_feature(enable = "avx512f")]
36#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
37#[cfg_attr(test, assert_instr(vcvtss2usi))]
38pub fn _mm_cvtss_u64(a: __m128) -> u64 {
39    unsafe { vcvtss2usi64(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION) }
40}
41
42/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.
43///
44/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsd_u64&expand=1800)
45#[inline]
46#[target_feature(enable = "avx512f")]
47#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
48#[cfg_attr(test, assert_instr(vcvtsd2usi))]
49pub fn _mm_cvtsd_u64(a: __m128d) -> u64 {
50    unsafe { vcvtsd2usi64(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION) }
51}
52
53/// Convert the signed 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
54///
55/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvti64_ss&expand=1643)
56#[inline]
57#[target_feature(enable = "avx512f")]
58#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
59#[cfg_attr(test, assert_instr(vcvtsi2ss))]
60pub fn _mm_cvti64_ss(a: __m128, b: i64) -> __m128 {
61    unsafe {
62        let b = b as f32;
63        simd_insert!(a, 0, b)
64    }
65}
66
67/// Convert the signed 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
68///
69/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvti64_sd&expand=1644)
70#[inline]
71#[target_feature(enable = "avx512f")]
72#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
73#[cfg_attr(test, assert_instr(vcvtsi2sd))]
74pub fn _mm_cvti64_sd(a: __m128d, b: i64) -> __m128d {
75    unsafe {
76        let b = b as f64;
77        simd_insert!(a, 0, b)
78    }
79}
80
81/// Convert the unsigned 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
82///
83/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtu64_ss&expand=2035)
84#[inline]
85#[target_feature(enable = "avx512f")]
86#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
87#[cfg_attr(test, assert_instr(vcvtusi2ss))]
88pub fn _mm_cvtu64_ss(a: __m128, b: u64) -> __m128 {
89    unsafe {
90        let b = b as f32;
91        simd_insert!(a, 0, b)
92    }
93}
94
95/// Convert the unsigned 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
96///
97/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtu64_sd&expand=2034)
98#[inline]
99#[target_feature(enable = "avx512f")]
100#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
101#[cfg_attr(test, assert_instr(vcvtusi2sd))]
102pub fn _mm_cvtu64_sd(a: __m128d, b: u64) -> __m128d {
103    unsafe {
104        let b = b as f64;
105        simd_insert!(a, 0, b)
106    }
107}
108
109/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.
110///
111/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttsd_i64&expand=2016)
112#[inline]
113#[target_feature(enable = "avx512f")]
114#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
115#[cfg_attr(test, assert_instr(vcvttsd2si))]
116pub fn _mm_cvttsd_i64(a: __m128d) -> i64 {
117    unsafe { vcvttsd2si64(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION) }
118}
119
120/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.
121///
122/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttsd_u64&expand=2021)
123#[inline]
124#[target_feature(enable = "avx512f")]
125#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
126#[cfg_attr(test, assert_instr(vcvttsd2usi))]
127pub fn _mm_cvttsd_u64(a: __m128d) -> u64 {
128    unsafe { vcvttsd2usi64(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION) }
129}
130
131/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.
132///
133/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=#text=_mm_cvttss_i64&expand=2023)
134#[inline]
135#[target_feature(enable = "avx512f")]
136#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
137#[cfg_attr(test, assert_instr(vcvttss2si))]
138pub fn _mm_cvttss_i64(a: __m128) -> i64 {
139    unsafe { vcvttss2si64(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION) }
140}
141
142/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.
143///
144/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttss_u64&expand=2027)
145#[inline]
146#[target_feature(enable = "avx512f")]
147#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
148#[cfg_attr(test, assert_instr(vcvttss2usi))]
149pub fn _mm_cvttss_u64(a: __m128) -> u64 {
150    unsafe { vcvttss2usi64(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION) }
151}
152
153/// Convert the signed 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
154/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
155/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
156/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
157/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
158/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
159/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
160///
161/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundi64_sd&expand=1313)
162#[inline]
163#[target_feature(enable = "avx512f")]
164#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
165#[cfg_attr(test, assert_instr(vcvtsi2sd, ROUNDING = 8))]
166#[rustc_legacy_const_generics(2)]
167pub fn _mm_cvt_roundi64_sd<const ROUNDING: i32>(a: __m128d, b: i64) -> __m128d {
168    unsafe {
169        static_assert_rounding!(ROUNDING);
170        let a = a.as_f64x2();
171        let r = vcvtsi2sd64(a, b, ROUNDING);
172        transmute(r)
173    }
174}
175
176/// Convert the signed 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
177/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
178/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
179/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
180/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
181/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
182/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
183///
184/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsi64_sd&expand=1367)
185#[inline]
186#[target_feature(enable = "avx512f")]
187#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
188#[cfg_attr(test, assert_instr(vcvtsi2sd, ROUNDING = 8))]
189#[rustc_legacy_const_generics(2)]
190pub fn _mm_cvt_roundsi64_sd<const ROUNDING: i32>(a: __m128d, b: i64) -> __m128d {
191    unsafe {
192        static_assert_rounding!(ROUNDING);
193        let a = a.as_f64x2();
194        let r = vcvtsi2sd64(a, b, ROUNDING);
195        transmute(r)
196    }
197}
198
199/// Convert the signed 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
200/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
201/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
202/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
203/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
204/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
205/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
206///
207/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundi64_ss&expand=1314)
208#[inline]
209#[target_feature(enable = "avx512f")]
210#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
211#[cfg_attr(test, assert_instr(vcvtsi2ss, ROUNDING = 8))]
212#[rustc_legacy_const_generics(2)]
213pub fn _mm_cvt_roundi64_ss<const ROUNDING: i32>(a: __m128, b: i64) -> __m128 {
214    unsafe {
215        static_assert_rounding!(ROUNDING);
216        let a = a.as_f32x4();
217        let r = vcvtsi2ss64(a, b, ROUNDING);
218        transmute(r)
219    }
220}
221
222/// Convert the unsigned 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.\
223/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
224/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
225/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
226/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
227/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
228/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
229///
230/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundu64_sd&expand=1379)
231#[inline]
232#[target_feature(enable = "avx512f")]
233#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
234#[cfg_attr(test, assert_instr(vcvtusi2sd, ROUNDING = 8))]
235#[rustc_legacy_const_generics(2)]
236pub fn _mm_cvt_roundu64_sd<const ROUNDING: i32>(a: __m128d, b: u64) -> __m128d {
237    unsafe {
238        static_assert_rounding!(ROUNDING);
239        let a = a.as_f64x2();
240        let r = vcvtusi2sd64(a, b, ROUNDING);
241        transmute(r)
242    }
243}
244
245/// Convert the signed 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
246/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
247/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
248/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
249/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
250/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
251/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
252///
253/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsi64_ss&expand=1368)
254#[inline]
255#[target_feature(enable = "avx512f")]
256#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
257#[cfg_attr(test, assert_instr(vcvtsi2ss, ROUNDING = 8))]
258#[rustc_legacy_const_generics(2)]
259pub fn _mm_cvt_roundsi64_ss<const ROUNDING: i32>(a: __m128, b: i64) -> __m128 {
260    unsafe {
261        static_assert_rounding!(ROUNDING);
262        let a = a.as_f32x4();
263        let r = vcvtsi2ss64(a, b, ROUNDING);
264        transmute(r)
265    }
266}
267
268/// Convert the unsigned 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.\
269/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
270/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
271/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
272/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
273/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
274/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
275///
276/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundu64_ss&expand=1380)
277#[inline]
278#[target_feature(enable = "avx512f")]
279#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
280#[cfg_attr(test, assert_instr(vcvtusi2ss, ROUNDING = 8))]
281#[rustc_legacy_const_generics(2)]
282pub fn _mm_cvt_roundu64_ss<const ROUNDING: i32>(a: __m128, b: u64) -> __m128 {
283    unsafe {
284        static_assert_rounding!(ROUNDING);
285        let a = a.as_f32x4();
286        let r = vcvtusi2ss64(a, b, ROUNDING);
287        transmute(r)
288    }
289}
290
291/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
292/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
293/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
294/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
295/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
296/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
297/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
298///
299/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_si64&expand=1360)
300#[inline]
301#[target_feature(enable = "avx512f")]
302#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
303#[cfg_attr(test, assert_instr(vcvtsd2si, ROUNDING = 8))]
304#[rustc_legacy_const_generics(1)]
305pub fn _mm_cvt_roundsd_si64<const ROUNDING: i32>(a: __m128d) -> i64 {
306    unsafe {
307        static_assert_rounding!(ROUNDING);
308        let a = a.as_f64x2();
309        vcvtsd2si64(a, ROUNDING)
310    }
311}
312
313/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
314/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
315/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
316/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
317/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
318/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
319/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
320///
321/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_i64&expand=1358)
322#[inline]
323#[target_feature(enable = "avx512f")]
324#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
325#[cfg_attr(test, assert_instr(vcvtsd2si, ROUNDING = 8))]
326#[rustc_legacy_const_generics(1)]
327pub fn _mm_cvt_roundsd_i64<const ROUNDING: i32>(a: __m128d) -> i64 {
328    unsafe {
329        static_assert_rounding!(ROUNDING);
330        let a = a.as_f64x2();
331        vcvtsd2si64(a, ROUNDING)
332    }
333}
334
335/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.\
336/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
337/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
338/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
339/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
340/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
341/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
342///
343/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_u64&expand=1365)
344#[inline]
345#[target_feature(enable = "avx512f")]
346#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
347#[cfg_attr(test, assert_instr(vcvtsd2usi, ROUNDING = 8))]
348#[rustc_legacy_const_generics(1)]
349pub fn _mm_cvt_roundsd_u64<const ROUNDING: i32>(a: __m128d) -> u64 {
350    unsafe {
351        static_assert_rounding!(ROUNDING);
352        let a = a.as_f64x2();
353        vcvtsd2usi64(a, ROUNDING)
354    }
355}
356
357/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
358/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
359/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
360/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
361/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
362/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
363/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
364///
365/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_si64&expand=1375)
366#[inline]
367#[target_feature(enable = "avx512f")]
368#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
369#[cfg_attr(test, assert_instr(vcvtss2si, ROUNDING = 8))]
370#[rustc_legacy_const_generics(1)]
371pub fn _mm_cvt_roundss_si64<const ROUNDING: i32>(a: __m128) -> i64 {
372    unsafe {
373        static_assert_rounding!(ROUNDING);
374        let a = a.as_f32x4();
375        vcvtss2si64(a, ROUNDING)
376    }
377}
378
379/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
380/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
381/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
382/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
383/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
384/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
385/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
386///
387/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_i64&expand=1370)
388#[inline]
389#[target_feature(enable = "avx512f")]
390#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
391#[cfg_attr(test, assert_instr(vcvtss2si, ROUNDING = 8))]
392#[rustc_legacy_const_generics(1)]
393pub fn _mm_cvt_roundss_i64<const ROUNDING: i32>(a: __m128) -> i64 {
394    unsafe {
395        static_assert_rounding!(ROUNDING);
396        let a = a.as_f32x4();
397        vcvtss2si64(a, ROUNDING)
398    }
399}
400
401/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.\
402/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
403/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
404/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
405/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
406/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
407/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
408///
409/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_u64&expand=1377)
410#[inline]
411#[target_feature(enable = "avx512f")]
412#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
413#[cfg_attr(test, assert_instr(vcvtss2usi, ROUNDING = 8))]
414#[rustc_legacy_const_generics(1)]
415pub fn _mm_cvt_roundss_u64<const ROUNDING: i32>(a: __m128) -> u64 {
416    unsafe {
417        static_assert_rounding!(ROUNDING);
418        let a = a.as_f32x4();
419        vcvtss2usi64(a, ROUNDING)
420    }
421}
422
423/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
424/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
425///
426/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_si64&expand=1931)
427#[inline]
428#[target_feature(enable = "avx512f")]
429#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
430#[cfg_attr(test, assert_instr(vcvttsd2si, SAE = 8))]
431#[rustc_legacy_const_generics(1)]
432pub fn _mm_cvtt_roundsd_si64<const SAE: i32>(a: __m128d) -> i64 {
433    unsafe {
434        static_assert_sae!(SAE);
435        let a = a.as_f64x2();
436        vcvttsd2si64(a, SAE)
437    }
438}
439
440/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
441/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
442///
443/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_i64&expand=1929)
444#[inline]
445#[target_feature(enable = "avx512f")]
446#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
447#[cfg_attr(test, assert_instr(vcvttsd2si, SAE = 8))]
448#[rustc_legacy_const_generics(1)]
449pub fn _mm_cvtt_roundsd_i64<const SAE: i32>(a: __m128d) -> i64 {
450    unsafe {
451        static_assert_sae!(SAE);
452        let a = a.as_f64x2();
453        vcvttsd2si64(a, SAE)
454    }
455}
456
457/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.\
458/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
459///
460/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_u64&expand=1933)
461#[inline]
462#[target_feature(enable = "avx512f")]
463#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
464#[cfg_attr(test, assert_instr(vcvttsd2usi, SAE = 8))]
465#[rustc_legacy_const_generics(1)]
466pub fn _mm_cvtt_roundsd_u64<const SAE: i32>(a: __m128d) -> u64 {
467    unsafe {
468        static_assert_sae!(SAE);
469        let a = a.as_f64x2();
470        vcvttsd2usi64(a, SAE)
471    }
472}
473
474/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
475/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
476///
477/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_i64&expand=1935)
478#[inline]
479#[target_feature(enable = "avx512f")]
480#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
481#[cfg_attr(test, assert_instr(vcvttss2si, SAE = 8))]
482#[rustc_legacy_const_generics(1)]
483pub fn _mm_cvtt_roundss_i64<const SAE: i32>(a: __m128) -> i64 {
484    unsafe {
485        static_assert_sae!(SAE);
486        let a = a.as_f32x4();
487        vcvttss2si64(a, SAE)
488    }
489}
490
491/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
492/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
493///
494/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_si64&expand=1937)
495#[inline]
496#[target_feature(enable = "avx512f")]
497#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
498#[cfg_attr(test, assert_instr(vcvttss2si, SAE = 8))]
499#[rustc_legacy_const_generics(1)]
500pub fn _mm_cvtt_roundss_si64<const SAE: i32>(a: __m128) -> i64 {
501    unsafe {
502        static_assert_sae!(SAE);
503        let a = a.as_f32x4();
504        vcvttss2si64(a, SAE)
505    }
506}
507
508/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.\
509/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
510///
511/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_u64&expand=1939)
512#[inline]
513#[target_feature(enable = "avx512f")]
514#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
515#[cfg_attr(test, assert_instr(vcvttss2usi, SAE = 8))]
516#[rustc_legacy_const_generics(1)]
517pub fn _mm_cvtt_roundss_u64<const SAE: i32>(a: __m128) -> u64 {
518    unsafe {
519        static_assert_sae!(SAE);
520        let a = a.as_f32x4();
521        vcvttss2usi64(a, SAE)
522    }
523}
524
525#[allow(improper_ctypes)]
526unsafe extern "C" {
527    #[link_name = "llvm.x86.avx512.vcvtss2si64"]
528    fn vcvtss2si64(a: f32x4, rounding: i32) -> i64;
529    #[link_name = "llvm.x86.avx512.vcvtss2usi64"]
530    fn vcvtss2usi64(a: f32x4, rounding: i32) -> u64;
531    #[link_name = "llvm.x86.avx512.vcvtsd2si64"]
532    fn vcvtsd2si64(a: f64x2, rounding: i32) -> i64;
533    #[link_name = "llvm.x86.avx512.vcvtsd2usi64"]
534    fn vcvtsd2usi64(a: f64x2, rounding: i32) -> u64;
535
536    #[link_name = "llvm.x86.avx512.cvtsi2ss64"]
537    fn vcvtsi2ss64(a: f32x4, b: i64, rounding: i32) -> f32x4;
538    #[link_name = "llvm.x86.avx512.cvtsi2sd64"]
539    fn vcvtsi2sd64(a: f64x2, b: i64, rounding: i32) -> f64x2;
540    #[link_name = "llvm.x86.avx512.cvtusi642ss"]
541    fn vcvtusi2ss64(a: f32x4, b: u64, rounding: i32) -> f32x4;
542    #[link_name = "llvm.x86.avx512.cvtusi642sd"]
543    fn vcvtusi2sd64(a: f64x2, b: u64, rounding: i32) -> f64x2;
544
545    #[link_name = "llvm.x86.avx512.cvttss2si64"]
546    fn vcvttss2si64(a: f32x4, rounding: i32) -> i64;
547    #[link_name = "llvm.x86.avx512.cvttss2usi64"]
548    fn vcvttss2usi64(a: f32x4, rounding: i32) -> u64;
549    #[link_name = "llvm.x86.avx512.cvttsd2si64"]
550    fn vcvttsd2si64(a: f64x2, rounding: i32) -> i64;
551    #[link_name = "llvm.x86.avx512.cvttsd2usi64"]
552    fn vcvttsd2usi64(a: f64x2, rounding: i32) -> u64;
553}
554
555#[cfg(test)]
556mod tests {
557
558    use stdarch_test::simd_test;
559
560    use crate::core_arch::x86::*;
561    use crate::core_arch::x86_64::*;
562    use crate::hint::black_box;
563
564    #[simd_test(enable = "avx512f")]
565    unsafe fn test_mm512_abs_epi64() {
566        let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
567        let r = _mm512_abs_epi64(a);
568        let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MAX.wrapping_add(1), 100, 100, 32);
569        assert_eq_m512i(r, e);
570    }
571
572    #[simd_test(enable = "avx512f")]
573    unsafe fn test_mm512_mask_abs_epi64() {
574        let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
575        let r = _mm512_mask_abs_epi64(a, 0, a);
576        assert_eq_m512i(r, a);
577        let r = _mm512_mask_abs_epi64(a, 0b11111111, a);
578        let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MIN, 100, 100, 32);
579        assert_eq_m512i(r, e);
580    }
581
582    #[simd_test(enable = "avx512f")]
583    unsafe fn test_mm512_maskz_abs_epi64() {
584        let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
585        let r = _mm512_maskz_abs_epi64(0, a);
586        assert_eq_m512i(r, _mm512_setzero_si512());
587        let r = _mm512_maskz_abs_epi64(0b11111111, a);
588        let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MIN, 100, 100, 32);
589        assert_eq_m512i(r, e);
590    }
591
592    #[simd_test(enable = "avx512f,avx512vl")]
593    unsafe fn test_mm256_abs_epi64() {
594        let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
595        let r = _mm256_abs_epi64(a);
596        let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
597        assert_eq_m256i(r, e);
598    }
599
600    #[simd_test(enable = "avx512f,avx512vl")]
601    unsafe fn test_mm256_mask_abs_epi64() {
602        let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
603        let r = _mm256_mask_abs_epi64(a, 0, a);
604        assert_eq_m256i(r, a);
605        let r = _mm256_mask_abs_epi64(a, 0b00001111, a);
606        let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
607        assert_eq_m256i(r, e);
608    }
609
610    #[simd_test(enable = "avx512f,avx512vl")]
611    unsafe fn test_mm256_maskz_abs_epi64() {
612        let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
613        let r = _mm256_maskz_abs_epi64(0, a);
614        assert_eq_m256i(r, _mm256_setzero_si256());
615        let r = _mm256_maskz_abs_epi64(0b00001111, a);
616        let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
617        assert_eq_m256i(r, e);
618    }
619
620    #[simd_test(enable = "avx512f,avx512vl")]
621    unsafe fn test_mm_abs_epi64() {
622        let a = _mm_set_epi64x(i64::MAX, i64::MIN);
623        let r = _mm_abs_epi64(a);
624        let e = _mm_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1));
625        assert_eq_m128i(r, e);
626        let a = _mm_set_epi64x(100, -100);
627        let r = _mm_abs_epi64(a);
628        let e = _mm_set_epi64x(100, 100);
629        assert_eq_m128i(r, e);
630    }
631
632    #[simd_test(enable = "avx512f,avx512vl")]
633    unsafe fn test_mm_mask_abs_epi64() {
634        let a = _mm_set_epi64x(i64::MAX, i64::MIN);
635        let r = _mm_mask_abs_epi64(a, 0, a);
636        assert_eq_m128i(r, a);
637        let r = _mm_mask_abs_epi64(a, 0b00000011, a);
638        let e = _mm_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1));
639        assert_eq_m128i(r, e);
640        let a = _mm_set_epi64x(100, -100);
641        let r = _mm_mask_abs_epi64(a, 0b00000011, a);
642        let e = _mm_set_epi64x(100, 100);
643        assert_eq_m128i(r, e);
644    }
645
646    #[simd_test(enable = "avx512f,avx512vl")]
647    unsafe fn test_mm_maskz_abs_epi64() {
648        let a = _mm_set_epi64x(i64::MAX, i64::MIN);
649        let r = _mm_maskz_abs_epi64(0, a);
650        assert_eq_m128i(r, _mm_setzero_si128());
651        let r = _mm_maskz_abs_epi64(0b00000011, a);
652        let e = _mm_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1));
653        assert_eq_m128i(r, e);
654        let a = _mm_set_epi64x(100, -100);
655        let r = _mm_maskz_abs_epi64(0b00000011, a);
656        let e = _mm_set_epi64x(100, 100);
657        assert_eq_m128i(r, e);
658    }
659
660    #[simd_test(enable = "avx512f")]
661    unsafe fn test_mm512_abs_pd() {
662        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
663        let r = _mm512_abs_pd(a);
664        let e = _mm512_setr_pd(0., 1., 1., f64::MAX, f64::MAX, 100., 100., 32.);
665        assert_eq_m512d(r, e);
666    }
667
668    #[simd_test(enable = "avx512f")]
669    unsafe fn test_mm512_mask_abs_pd() {
670        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
671        let r = _mm512_mask_abs_pd(a, 0, a);
672        assert_eq_m512d(r, a);
673        let r = _mm512_mask_abs_pd(a, 0b00001111, a);
674        let e = _mm512_setr_pd(0., 1., 1., f64::MAX, f64::MIN, 100., -100., -32.);
675        assert_eq_m512d(r, e);
676    }
677
678    #[simd_test(enable = "avx512f")]
679    unsafe fn test_mm512_mask_mov_epi64() {
680        let src = _mm512_set1_epi64(1);
681        let a = _mm512_set1_epi64(2);
682        let r = _mm512_mask_mov_epi64(src, 0, a);
683        assert_eq_m512i(r, src);
684        let r = _mm512_mask_mov_epi64(src, 0b11111111, a);
685        assert_eq_m512i(r, a);
686    }
687
688    #[simd_test(enable = "avx512f")]
689    unsafe fn test_mm512_maskz_mov_epi64() {
690        let a = _mm512_set1_epi64(2);
691        let r = _mm512_maskz_mov_epi64(0, a);
692        assert_eq_m512i(r, _mm512_setzero_si512());
693        let r = _mm512_maskz_mov_epi64(0b11111111, a);
694        assert_eq_m512i(r, a);
695    }
696
697    #[simd_test(enable = "avx512f,avx512vl")]
698    unsafe fn test_mm256_mask_mov_epi64() {
699        let src = _mm256_set1_epi64x(1);
700        let a = _mm256_set1_epi64x(2);
701        let r = _mm256_mask_mov_epi64(src, 0, a);
702        assert_eq_m256i(r, src);
703        let r = _mm256_mask_mov_epi64(src, 0b00001111, a);
704        assert_eq_m256i(r, a);
705    }
706
707    #[simd_test(enable = "avx512f,avx512vl")]
708    unsafe fn test_mm256_maskz_mov_epi64() {
709        let a = _mm256_set1_epi64x(2);
710        let r = _mm256_maskz_mov_epi64(0, a);
711        assert_eq_m256i(r, _mm256_setzero_si256());
712        let r = _mm256_maskz_mov_epi64(0b00001111, a);
713        assert_eq_m256i(r, a);
714    }
715
716    #[simd_test(enable = "avx512f,avx512vl")]
717    unsafe fn test_mm_mask_mov_epi64() {
718        let src = _mm_set1_epi64x(1);
719        let a = _mm_set1_epi64x(2);
720        let r = _mm_mask_mov_epi64(src, 0, a);
721        assert_eq_m128i(r, src);
722        let r = _mm_mask_mov_epi64(src, 0b00000011, a);
723        assert_eq_m128i(r, a);
724    }
725
726    #[simd_test(enable = "avx512f,avx512vl")]
727    unsafe fn test_mm_maskz_mov_epi64() {
728        let a = _mm_set1_epi64x(2);
729        let r = _mm_maskz_mov_epi64(0, a);
730        assert_eq_m128i(r, _mm_setzero_si128());
731        let r = _mm_maskz_mov_epi64(0b00000011, a);
732        assert_eq_m128i(r, a);
733    }
734
735    #[simd_test(enable = "avx512f")]
736    unsafe fn test_mm512_mask_mov_pd() {
737        let src = _mm512_set1_pd(1.);
738        let a = _mm512_set1_pd(2.);
739        let r = _mm512_mask_mov_pd(src, 0, a);
740        assert_eq_m512d(r, src);
741        let r = _mm512_mask_mov_pd(src, 0b11111111, a);
742        assert_eq_m512d(r, a);
743    }
744
745    #[simd_test(enable = "avx512f")]
746    unsafe fn test_mm512_maskz_mov_pd() {
747        let a = _mm512_set1_pd(2.);
748        let r = _mm512_maskz_mov_pd(0, a);
749        assert_eq_m512d(r, _mm512_setzero_pd());
750        let r = _mm512_maskz_mov_pd(0b11111111, a);
751        assert_eq_m512d(r, a);
752    }
753
754    #[simd_test(enable = "avx512f,avx512vl")]
755    unsafe fn test_mm256_mask_mov_pd() {
756        let src = _mm256_set1_pd(1.);
757        let a = _mm256_set1_pd(2.);
758        let r = _mm256_mask_mov_pd(src, 0, a);
759        assert_eq_m256d(r, src);
760        let r = _mm256_mask_mov_pd(src, 0b00001111, a);
761        assert_eq_m256d(r, a);
762    }
763
764    #[simd_test(enable = "avx512f,avx512vl")]
765    unsafe fn test_mm256_maskz_mov_pd() {
766        let a = _mm256_set1_pd(2.);
767        let r = _mm256_maskz_mov_pd(0, a);
768        assert_eq_m256d(r, _mm256_setzero_pd());
769        let r = _mm256_maskz_mov_pd(0b00001111, a);
770        assert_eq_m256d(r, a);
771    }
772
773    #[simd_test(enable = "avx512f,avx512vl")]
774    unsafe fn test_mm_mask_mov_pd() {
775        let src = _mm_set1_pd(1.);
776        let a = _mm_set1_pd(2.);
777        let r = _mm_mask_mov_pd(src, 0, a);
778        assert_eq_m128d(r, src);
779        let r = _mm_mask_mov_pd(src, 0b00000011, a);
780        assert_eq_m128d(r, a);
781    }
782
783    #[simd_test(enable = "avx512f,avx512vl")]
784    unsafe fn test_mm_maskz_mov_pd() {
785        let a = _mm_set1_pd(2.);
786        let r = _mm_maskz_mov_pd(0, a);
787        assert_eq_m128d(r, _mm_setzero_pd());
788        let r = _mm_maskz_mov_pd(0b00000011, a);
789        assert_eq_m128d(r, a);
790    }
791
792    #[simd_test(enable = "avx512f")]
793    unsafe fn test_mm512_add_epi64() {
794        let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
795        let b = _mm512_set1_epi64(1);
796        let r = _mm512_add_epi64(a, b);
797        let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, i64::MIN + 1, 101, -99, -31);
798        assert_eq_m512i(r, e);
799    }
800
801    #[simd_test(enable = "avx512f")]
802    unsafe fn test_mm512_mask_add_epi64() {
803        let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
804        let b = _mm512_set1_epi64(1);
805        let r = _mm512_mask_add_epi64(a, 0, a, b);
806        assert_eq_m512i(r, a);
807        let r = _mm512_mask_add_epi64(a, 0b00001111, a, b);
808        let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, i64::MIN, 100, -100, -32);
809        assert_eq_m512i(r, e);
810    }
811
812    #[simd_test(enable = "avx512f")]
813    unsafe fn test_mm512_maskz_add_epi64() {
814        let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
815        let b = _mm512_set1_epi64(1);
816        let r = _mm512_maskz_add_epi64(0, a, b);
817        assert_eq_m512i(r, _mm512_setzero_si512());
818        let r = _mm512_maskz_add_epi64(0b00001111, a, b);
819        let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, 0, 0, 0, 0);
820        assert_eq_m512i(r, e);
821    }
822
823    #[simd_test(enable = "avx512f,avx512vl")]
824    unsafe fn test_mm256_mask_add_epi64() {
825        let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
826        let b = _mm256_set1_epi64x(1);
827        let r = _mm256_mask_add_epi64(a, 0, a, b);
828        assert_eq_m256i(r, a);
829        let r = _mm256_mask_add_epi64(a, 0b00001111, a, b);
830        let e = _mm256_set_epi64x(2, 0, i64::MIN, i64::MIN + 1);
831        assert_eq_m256i(r, e);
832    }
833
834    #[simd_test(enable = "avx512f,avx512vl")]
835    unsafe fn test_mm256_maskz_add_epi64() {
836        let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
837        let b = _mm256_set1_epi64x(1);
838        let r = _mm256_maskz_add_epi64(0, a, b);
839        assert_eq_m256i(r, _mm256_setzero_si256());
840        let r = _mm256_maskz_add_epi64(0b00001111, a, b);
841        let e = _mm256_set_epi64x(2, 0, i64::MIN, i64::MIN + 1);
842        assert_eq_m256i(r, e);
843    }
844
845    #[simd_test(enable = "avx512f,avx512vl")]
846    unsafe fn test_mm_mask_add_epi64() {
847        let a = _mm_set_epi64x(i64::MAX, i64::MIN);
848        let b = _mm_set1_epi64x(1);
849        let r = _mm_mask_add_epi64(a, 0, a, b);
850        assert_eq_m128i(r, a);
851        let r = _mm_mask_add_epi64(a, 0b00000011, a, b);
852        let e = _mm_set_epi64x(i64::MIN, i64::MIN + 1);
853        assert_eq_m128i(r, e);
854    }
855
856    #[simd_test(enable = "avx512f,avx512vl")]
857    unsafe fn test_mm_maskz_add_epi64() {
858        let a = _mm_set_epi64x(i64::MAX, i64::MIN);
859        let b = _mm_set1_epi64x(1);
860        let r = _mm_maskz_add_epi64(0, a, b);
861        assert_eq_m128i(r, _mm_setzero_si128());
862        let r = _mm_maskz_add_epi64(0b00000011, a, b);
863        let e = _mm_set_epi64x(i64::MIN, i64::MIN + 1);
864        assert_eq_m128i(r, e);
865    }
866
867    #[simd_test(enable = "avx512f")]
868    unsafe fn test_mm512_add_pd() {
869        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
870        let b = _mm512_set1_pd(1.);
871        let r = _mm512_add_pd(a, b);
872        let e = _mm512_setr_pd(1., 2., 0., f64::MAX, f64::MIN + 1., 101., -99., -31.);
873        assert_eq_m512d(r, e);
874    }
875
876    #[simd_test(enable = "avx512f")]
877    unsafe fn test_mm512_mask_add_pd() {
878        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
879        let b = _mm512_set1_pd(1.);
880        let r = _mm512_mask_add_pd(a, 0, a, b);
881        assert_eq_m512d(r, a);
882        let r = _mm512_mask_add_pd(a, 0b00001111, a, b);
883        let e = _mm512_setr_pd(1., 2., 0., f64::MAX, f64::MIN, 100., -100., -32.);
884        assert_eq_m512d(r, e);
885    }
886
887    #[simd_test(enable = "avx512f")]
888    unsafe fn test_mm512_maskz_add_pd() {
889        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
890        let b = _mm512_set1_pd(1.);
891        let r = _mm512_maskz_add_pd(0, a, b);
892        assert_eq_m512d(r, _mm512_setzero_pd());
893        let r = _mm512_maskz_add_pd(0b00001111, a, b);
894        let e = _mm512_setr_pd(1., 2., 0., f64::MAX, 0., 0., 0., 0.);
895        assert_eq_m512d(r, e);
896    }
897
898    #[simd_test(enable = "avx512f,avx512vl")]
899    unsafe fn test_mm256_mask_add_pd() {
900        let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
901        let b = _mm256_set1_pd(1.);
902        let r = _mm256_mask_add_pd(a, 0, a, b);
903        assert_eq_m256d(r, a);
904        let r = _mm256_mask_add_pd(a, 0b00001111, a, b);
905        let e = _mm256_set_pd(2., 0., f64::MAX, f64::MIN + 1.);
906        assert_eq_m256d(r, e);
907    }
908
909    #[simd_test(enable = "avx512f,avx512vl")]
910    unsafe fn test_mm256_maskz_add_pd() {
911        let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
912        let b = _mm256_set1_pd(1.);
913        let r = _mm256_maskz_add_pd(0, a, b);
914        assert_eq_m256d(r, _mm256_setzero_pd());
915        let r = _mm256_maskz_add_pd(0b00001111, a, b);
916        let e = _mm256_set_pd(2., 0., f64::MAX, f64::MIN + 1.);
917        assert_eq_m256d(r, e);
918    }
919
920    #[simd_test(enable = "avx512f,avx512vl")]
921    unsafe fn test_mm_mask_add_pd() {
922        let a = _mm_set_pd(f64::MAX, f64::MIN);
923        let b = _mm_set1_pd(1.);
924        let r = _mm_mask_add_pd(a, 0, a, b);
925        assert_eq_m128d(r, a);
926        let r = _mm_mask_add_pd(a, 0b00000011, a, b);
927        let e = _mm_set_pd(f64::MAX, f64::MIN + 1.);
928        assert_eq_m128d(r, e);
929    }
930
931    #[simd_test(enable = "avx512f,avx512vl")]
932    unsafe fn test_mm_maskz_add_pd() {
933        let a = _mm_set_pd(f64::MAX, f64::MIN);
934        let b = _mm_set1_pd(1.);
935        let r = _mm_maskz_add_pd(0, a, b);
936        assert_eq_m128d(r, _mm_setzero_pd());
937        let r = _mm_maskz_add_pd(0b00000011, a, b);
938        let e = _mm_set_pd(f64::MAX, f64::MIN + 1.);
939        assert_eq_m128d(r, e);
940    }
941
942    #[simd_test(enable = "avx512f")]
943    unsafe fn test_mm512_sub_epi64() {
944        let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
945        let b = _mm512_set1_epi64(1);
946        let r = _mm512_sub_epi64(a, b);
947        let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, i64::MAX, 99, -101, -33);
948        assert_eq_m512i(r, e);
949    }
950
951    #[simd_test(enable = "avx512f")]
952    unsafe fn test_mm512_mask_sub_epi64() {
953        let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
954        let b = _mm512_set1_epi64(1);
955        let r = _mm512_mask_sub_epi64(a, 0, a, b);
956        assert_eq_m512i(r, a);
957        let r = _mm512_mask_sub_epi64(a, 0b00001111, a, b);
958        let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, i64::MIN, 100, -100, -32);
959        assert_eq_m512i(r, e);
960    }
961
962    #[simd_test(enable = "avx512f")]
963    unsafe fn test_mm512_maskz_sub_epi64() {
964        let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
965        let b = _mm512_set1_epi64(1);
966        let r = _mm512_maskz_sub_epi64(0, a, b);
967        assert_eq_m512i(r, _mm512_setzero_si512());
968        let r = _mm512_maskz_sub_epi64(0b00001111, a, b);
969        let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, 0, 0, 0, 0);
970        assert_eq_m512i(r, e);
971    }
972
973    #[simd_test(enable = "avx512f,avx512vl")]
974    unsafe fn test_mm256_mask_sub_epi64() {
975        let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
976        let b = _mm256_set1_epi64x(1);
977        let r = _mm256_mask_sub_epi64(a, 0, a, b);
978        assert_eq_m256i(r, a);
979        let r = _mm256_mask_sub_epi64(a, 0b00001111, a, b);
980        let e = _mm256_set_epi64x(0, -2, i64::MAX - 1, i64::MAX);
981        assert_eq_m256i(r, e);
982    }
983
984    #[simd_test(enable = "avx512f,avx512vl")]
985    unsafe fn test_mm256_maskz_sub_epi64() {
986        let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
987        let b = _mm256_set1_epi64x(1);
988        let r = _mm256_maskz_sub_epi64(0, a, b);
989        assert_eq_m256i(r, _mm256_setzero_si256());
990        let r = _mm256_maskz_sub_epi64(0b00001111, a, b);
991        let e = _mm256_set_epi64x(0, -2, i64::MAX - 1, i64::MAX);
992        assert_eq_m256i(r, e);
993    }
994
995    #[simd_test(enable = "avx512f,avx512vl")]
996    unsafe fn test_mm_mask_sub_epi64() {
997        let a = _mm_set_epi64x(i64::MAX, i64::MIN);
998        let b = _mm_set1_epi64x(1);
999        let r = _mm_mask_sub_epi64(a, 0, a, b);
1000        assert_eq_m128i(r, a);
1001        let r = _mm_mask_sub_epi64(a, 0b00000011, a, b);
1002        let e = _mm_set_epi64x(i64::MAX - 1, i64::MAX);
1003        assert_eq_m128i(r, e);
1004    }
1005
1006    #[simd_test(enable = "avx512f,avx512vl")]
1007    unsafe fn test_mm_maskz_sub_epi64() {
1008        let a = _mm_set_epi64x(i64::MAX, i64::MIN);
1009        let b = _mm_set1_epi64x(1);
1010        let r = _mm_maskz_sub_epi64(0, a, b);
1011        assert_eq_m128i(r, _mm_setzero_si128());
1012        let r = _mm_maskz_sub_epi64(0b00000011, a, b);
1013        let e = _mm_set_epi64x(i64::MAX - 1, i64::MAX);
1014        assert_eq_m128i(r, e);
1015    }
1016
1017    #[simd_test(enable = "avx512f")]
1018    unsafe fn test_mm512_sub_pd() {
1019        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
1020        let b = _mm512_set1_pd(1.);
1021        let r = _mm512_sub_pd(a, b);
1022        let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., f64::MIN, 99., -101., -33.);
1023        assert_eq_m512d(r, e);
1024    }
1025
1026    #[simd_test(enable = "avx512f")]
1027    unsafe fn test_mm512_mask_sub_pd() {
1028        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
1029        let b = _mm512_set1_pd(1.);
1030        let r = _mm512_mask_sub_pd(a, 0, a, b);
1031        assert_eq_m512d(r, a);
1032        let r = _mm512_mask_sub_pd(a, 0b00001111, a, b);
1033        let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., f64::MIN, 100., -100., -32.);
1034        assert_eq_m512d(r, e);
1035    }
1036
1037    #[simd_test(enable = "avx512f")]
1038    unsafe fn test_mm512_maskz_sub_pd() {
1039        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
1040        let b = _mm512_set1_pd(1.);
1041        let r = _mm512_maskz_sub_pd(0, a, b);
1042        assert_eq_m512d(r, _mm512_setzero_pd());
1043        let r = _mm512_maskz_sub_pd(0b00001111, a, b);
1044        let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., 0., 0., 0., 0.);
1045        assert_eq_m512d(r, e);
1046    }
1047
1048    #[simd_test(enable = "avx512f,avx512vl")]
1049    unsafe fn test_mm256_mask_sub_pd() {
1050        let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
1051        let b = _mm256_set1_pd(1.);
1052        let r = _mm256_mask_sub_pd(a, 0, a, b);
1053        assert_eq_m256d(r, a);
1054        let r = _mm256_mask_sub_pd(a, 0b00001111, a, b);
1055        let e = _mm256_set_pd(0., -2., f64::MAX - 1., f64::MIN);
1056        assert_eq_m256d(r, e);
1057    }
1058
1059    #[simd_test(enable = "avx512f,avx512vl")]
1060    unsafe fn test_mm256_maskz_sub_pd() {
1061        let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
1062        let b = _mm256_set1_pd(1.);
1063        let r = _mm256_maskz_sub_pd(0, a, b);
1064        assert_eq_m256d(r, _mm256_setzero_pd());
1065        let r = _mm256_maskz_sub_pd(0b00001111, a, b);
1066        let e = _mm256_set_pd(0., -2., f64::MAX - 1., f64::MIN);
1067        assert_eq_m256d(r, e);
1068    }
1069
1070    #[simd_test(enable = "avx512f,avx512vl")]
1071    unsafe fn test_mm_mask_sub_pd() {
1072        let a = _mm_set_pd(f64::MAX, f64::MIN);
1073        let b = _mm_set1_pd(1.);
1074        let r = _mm_mask_sub_pd(a, 0, a, b);
1075        assert_eq_m128d(r, a);
1076        let r = _mm_mask_sub_pd(a, 0b00000011, a, b);
1077        let e = _mm_set_pd(f64::MAX - 1., f64::MIN);
1078        assert_eq_m128d(r, e);
1079    }
1080
1081    #[simd_test(enable = "avx512f,avx512vl")]
1082    unsafe fn test_mm_maskz_sub_pd() {
1083        let a = _mm_set_pd(f64::MAX, f64::MIN);
1084        let b = _mm_set1_pd(1.);
1085        let r = _mm_maskz_sub_pd(0, a, b);
1086        assert_eq_m128d(r, _mm_setzero_pd());
1087        let r = _mm_maskz_sub_pd(0b00000011, a, b);
1088        let e = _mm_set_pd(f64::MAX - 1., f64::MIN);
1089        assert_eq_m128d(r, e);
1090    }
1091
1092    #[simd_test(enable = "avx512f")]
1093    unsafe fn test_mm512_mul_epi32() {
1094        let a = _mm512_set1_epi32(1);
1095        let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1096        let r = _mm512_mul_epi32(a, b);
1097        let e = _mm512_set_epi64(15, 13, 11, 9, 7, 5, 3, 1);
1098        assert_eq_m512i(r, e);
1099    }
1100
1101    #[simd_test(enable = "avx512f")]
1102    unsafe fn test_mm512_mask_mul_epi32() {
1103        let a = _mm512_set1_epi32(1);
1104        let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1105        let r = _mm512_mask_mul_epi32(a, 0, a, b);
1106        assert_eq_m512i(r, a);
1107        let r = _mm512_mask_mul_epi32(a, 0b00001111, a, b);
1108        #[rustfmt::skip]
1109        let e = _mm512_set_epi64(
1110            1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32,
1111            7, 5, 3, 1,
1112        );
1113        assert_eq_m512i(r, e);
1114    }
1115
1116    #[simd_test(enable = "avx512f")]
1117    unsafe fn test_mm512_maskz_mul_epi32() {
1118        let a = _mm512_set1_epi32(1);
1119        let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1120        let r = _mm512_maskz_mul_epi32(0, a, b);
1121        assert_eq_m512i(r, _mm512_setzero_si512());
1122        let r = _mm512_maskz_mul_epi32(0b00001111, a, b);
1123        let e = _mm512_set_epi64(0, 0, 0, 0, 7, 5, 3, 1);
1124        assert_eq_m512i(r, e);
1125    }
1126
1127    #[simd_test(enable = "avx512f,avx512vl")]
1128    unsafe fn test_mm256_mask_mul_epi32() {
1129        let a = _mm256_set1_epi32(1);
1130        let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1131        let r = _mm256_mask_mul_epi32(a, 0, a, b);
1132        assert_eq_m256i(r, a);
1133        let r = _mm256_mask_mul_epi32(a, 0b00001111, a, b);
1134        let e = _mm256_set_epi64x(2, 4, 6, 8);
1135        assert_eq_m256i(r, e);
1136    }
1137
1138    #[simd_test(enable = "avx512f,avx512vl")]
1139    unsafe fn test_mm256_maskz_mul_epi32() {
1140        let a = _mm256_set1_epi32(1);
1141        let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1142        let r = _mm256_maskz_mul_epi32(0, a, b);
1143        assert_eq_m256i(r, _mm256_setzero_si256());
1144        let r = _mm256_maskz_mul_epi32(0b00001111, a, b);
1145        let e = _mm256_set_epi64x(2, 4, 6, 8);
1146        assert_eq_m256i(r, e);
1147    }
1148
1149    #[simd_test(enable = "avx512f,avx512vl")]
1150    unsafe fn test_mm_mask_mul_epi32() {
1151        let a = _mm_set1_epi32(1);
1152        let b = _mm_set_epi32(1, 2, 3, 4);
1153        let r = _mm_mask_mul_epi32(a, 0, a, b);
1154        assert_eq_m128i(r, a);
1155        let r = _mm_mask_mul_epi32(a, 0b00000011, a, b);
1156        let e = _mm_set_epi64x(2, 4);
1157        assert_eq_m128i(r, e);
1158    }
1159
1160    #[simd_test(enable = "avx512f,avx512vl")]
1161    unsafe fn test_mm_maskz_mul_epi32() {
1162        let a = _mm_set1_epi32(1);
1163        let b = _mm_set_epi32(1, 2, 3, 4);
1164        let r = _mm_maskz_mul_epi32(0, a, b);
1165        assert_eq_m128i(r, _mm_setzero_si128());
1166        let r = _mm_maskz_mul_epi32(0b00000011, a, b);
1167        let e = _mm_set_epi64x(2, 4);
1168        assert_eq_m128i(r, e);
1169    }
1170
1171    #[simd_test(enable = "avx512f")]
1172    unsafe fn test_mm512_mul_epu32() {
1173        let a = _mm512_set1_epi32(1);
1174        let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1175        let r = _mm512_mul_epu32(a, b);
1176        let e = _mm512_set_epi64(15, 13, 11, 9, 7, 5, 3, 1);
1177        assert_eq_m512i(r, e);
1178    }
1179
1180    #[simd_test(enable = "avx512f")]
1181    unsafe fn test_mm512_mask_mul_epu32() {
1182        let a = _mm512_set1_epi32(1);
1183        let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1184        let r = _mm512_mask_mul_epu32(a, 0, a, b);
1185        assert_eq_m512i(r, a);
1186        let r = _mm512_mask_mul_epu32(a, 0b00001111, a, b);
1187        #[rustfmt::skip]
1188        let e = _mm512_set_epi64(
1189            1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32,
1190            7, 5, 3, 1,
1191        );
1192        assert_eq_m512i(r, e);
1193    }
1194
1195    #[simd_test(enable = "avx512f")]
1196    unsafe fn test_mm512_maskz_mul_epu32() {
1197        let a = _mm512_set1_epi32(1);
1198        let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1199        let r = _mm512_maskz_mul_epu32(0, a, b);
1200        assert_eq_m512i(r, _mm512_setzero_si512());
1201        let r = _mm512_maskz_mul_epu32(0b00001111, a, b);
1202        let e = _mm512_set_epi64(0, 0, 0, 0, 7, 5, 3, 1);
1203        assert_eq_m512i(r, e);
1204    }
1205
1206    #[simd_test(enable = "avx512f,avx512vl")]
1207    unsafe fn test_mm256_mask_mul_epu32() {
1208        let a = _mm256_set1_epi32(1);
1209        let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1210        let r = _mm256_mask_mul_epu32(a, 0, a, b);
1211        assert_eq_m256i(r, a);
1212        let r = _mm256_mask_mul_epu32(a, 0b00001111, a, b);
1213        let e = _mm256_set_epi64x(2, 4, 6, 8);
1214        assert_eq_m256i(r, e);
1215    }
1216
1217    #[simd_test(enable = "avx512f,avx512vl")]
1218    unsafe fn test_mm256_maskz_mul_epu32() {
1219        let a = _mm256_set1_epi32(1);
1220        let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1221        let r = _mm256_maskz_mul_epu32(0, a, b);
1222        assert_eq_m256i(r, _mm256_setzero_si256());
1223        let r = _mm256_maskz_mul_epu32(0b00001111, a, b);
1224        let e = _mm256_set_epi64x(2, 4, 6, 8);
1225        assert_eq_m256i(r, e);
1226    }
1227
1228    #[simd_test(enable = "avx512f,avx512vl")]
1229    unsafe fn test_mm_mask_mul_epu32() {
1230        let a = _mm_set1_epi32(1);
1231        let b = _mm_set_epi32(1, 2, 3, 4);
1232        let r = _mm_mask_mul_epu32(a, 0, a, b);
1233        assert_eq_m128i(r, a);
1234        let r = _mm_mask_mul_epu32(a, 0b00000011, a, b);
1235        let e = _mm_set_epi64x(2, 4);
1236        assert_eq_m128i(r, e);
1237    }
1238
1239    #[simd_test(enable = "avx512f,avx512vl")]
1240    unsafe fn test_mm_maskz_mul_epu32() {
1241        let a = _mm_set1_epi32(1);
1242        let b = _mm_set_epi32(1, 2, 3, 4);
1243        let r = _mm_maskz_mul_epu32(0, a, b);
1244        assert_eq_m128i(r, _mm_setzero_si128());
1245        let r = _mm_maskz_mul_epu32(0b00000011, a, b);
1246        let e = _mm_set_epi64x(2, 4);
1247        assert_eq_m128i(r, e);
1248    }
1249
1250    #[simd_test(enable = "avx512f")]
1251    unsafe fn test_mm512_mullox_epi64() {
1252        let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
1253        let b = _mm512_set1_epi64(2);
1254        let r = _mm512_mullox_epi64(a, b);
1255        let e = _mm512_setr_epi64(0, 2, -2, 0, -2, 200, -200, -64);
1256        assert_eq_m512i(r, e);
1257    }
1258
1259    #[simd_test(enable = "avx512f")]
1260    unsafe fn test_mm512_mask_mullox_epi64() {
1261        let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
1262        let b = _mm512_set1_epi64(2);
1263        let r = _mm512_mask_mullox_epi64(a, 0, a, b);
1264        assert_eq_m512i(r, a);
1265        let r = _mm512_mask_mullox_epi64(a, 0b00001111, a, b);
1266        let e = _mm512_setr_epi64(0, 2, -2, 0, i64::MAX, 100, -100, -32);
1267        assert_eq_m512i(r, e);
1268    }
1269
1270    #[simd_test(enable = "avx512f")]
1271    unsafe fn test_mm512_mul_pd() {
1272        let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1273        let b = _mm512_set1_pd(2.);
1274        let r = _mm512_mul_pd(a, b);
1275        #[rustfmt::skip]
1276        let e = _mm512_setr_pd(
1277            0., 2., f64::INFINITY, f64::NEG_INFINITY,
1278            f64::INFINITY, f64::NEG_INFINITY, -200., -64.,
1279        );
1280        assert_eq_m512d(r, e);
1281    }
1282
1283    #[simd_test(enable = "avx512f")]
1284    unsafe fn test_mm512_mask_mul_pd() {
1285        let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1286        let b = _mm512_set1_pd(2.);
1287        let r = _mm512_mask_mul_pd(a, 0, a, b);
1288        assert_eq_m512d(r, a);
1289        let r = _mm512_mask_mul_pd(a, 0b00001111, a, b);
1290        #[rustfmt::skip]
1291        let e = _mm512_setr_pd(
1292            0., 2., f64::INFINITY, f64::NEG_INFINITY,
1293            f64::MAX, f64::MIN, -100., -32.,
1294        );
1295        assert_eq_m512d(r, e);
1296    }
1297
1298    #[simd_test(enable = "avx512f")]
1299    unsafe fn test_mm512_maskz_mul_pd() {
1300        let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1301        let b = _mm512_set1_pd(2.);
1302        let r = _mm512_maskz_mul_pd(0, a, b);
1303        assert_eq_m512d(r, _mm512_setzero_pd());
1304        let r = _mm512_maskz_mul_pd(0b00001111, a, b);
1305        let e = _mm512_setr_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY, 0., 0., 0., 0.);
1306        assert_eq_m512d(r, e);
1307    }
1308
1309    #[simd_test(enable = "avx512f,avx512vl")]
1310    unsafe fn test_mm256_mask_mul_pd() {
1311        let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1312        let b = _mm256_set1_pd(2.);
1313        let r = _mm256_mask_mul_pd(a, 0, a, b);
1314        assert_eq_m256d(r, a);
1315        let r = _mm256_mask_mul_pd(a, 0b00001111, a, b);
1316        let e = _mm256_set_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY);
1317        assert_eq_m256d(r, e);
1318    }
1319
1320    #[simd_test(enable = "avx512f,avx512vl")]
1321    unsafe fn test_mm256_maskz_mul_pd() {
1322        let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1323        let b = _mm256_set1_pd(2.);
1324        let r = _mm256_maskz_mul_pd(0, a, b);
1325        assert_eq_m256d(r, _mm256_setzero_pd());
1326        let r = _mm256_maskz_mul_pd(0b00001111, a, b);
1327        let e = _mm256_set_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY);
1328        assert_eq_m256d(r, e);
1329    }
1330
1331    #[simd_test(enable = "avx512f,avx512vl")]
1332    unsafe fn test_mm_mask_mul_pd() {
1333        let a = _mm_set_pd(f64::MAX, f64::MIN);
1334        let b = _mm_set1_pd(2.);
1335        let r = _mm_mask_mul_pd(a, 0, a, b);
1336        assert_eq_m128d(r, a);
1337        let r = _mm_mask_mul_pd(a, 0b00000011, a, b);
1338        let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1339        assert_eq_m128d(r, e);
1340    }
1341
1342    #[simd_test(enable = "avx512f,avx512vl")]
1343    unsafe fn test_mm_maskz_mul_pd() {
1344        let a = _mm_set_pd(f64::MAX, f64::MIN);
1345        let b = _mm_set1_pd(2.);
1346        let r = _mm_maskz_mul_pd(0, a, b);
1347        assert_eq_m128d(r, _mm_setzero_pd());
1348        let r = _mm_maskz_mul_pd(0b00000011, a, b);
1349        let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1350        assert_eq_m128d(r, e);
1351    }
1352
1353    #[simd_test(enable = "avx512f")]
1354    unsafe fn test_mm512_div_pd() {
1355        let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1356        let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1357        let r = _mm512_div_pd(a, b);
1358        #[rustfmt::skip]
1359        let e = _mm512_setr_pd(
1360            0., 0.5, f64::INFINITY, f64::NEG_INFINITY,
1361            f64::INFINITY, f64::NEG_INFINITY, -50., -16.,
1362        );
1363        assert_eq_m512d(r, e);
1364    }
1365
1366    #[simd_test(enable = "avx512f")]
1367    unsafe fn test_mm512_mask_div_pd() {
1368        let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1369        let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1370        let r = _mm512_mask_div_pd(a, 0, a, b);
1371        assert_eq_m512d(r, a);
1372        let r = _mm512_mask_div_pd(a, 0b00001111, a, b);
1373        #[rustfmt::skip]
1374        let e = _mm512_setr_pd(
1375            0., 0.5, f64::INFINITY, f64::NEG_INFINITY,
1376            f64::MAX, f64::MIN, -100., -32.,
1377        );
1378        assert_eq_m512d(r, e);
1379    }
1380
1381    #[simd_test(enable = "avx512f")]
1382    unsafe fn test_mm512_maskz_div_pd() {
1383        let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1384        let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1385        let r = _mm512_maskz_div_pd(0, a, b);
1386        assert_eq_m512d(r, _mm512_setzero_pd());
1387        let r = _mm512_maskz_div_pd(0b00001111, a, b);
1388        let e = _mm512_setr_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY, 0., 0., 0., 0.);
1389        assert_eq_m512d(r, e);
1390    }
1391
1392    #[simd_test(enable = "avx512f,avx512vl")]
1393    unsafe fn test_mm256_mask_div_pd() {
1394        let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1395        let b = _mm256_set_pd(2., 2., 0., 0.);
1396        let r = _mm256_mask_div_pd(a, 0, a, b);
1397        assert_eq_m256d(r, a);
1398        let r = _mm256_mask_div_pd(a, 0b00001111, a, b);
1399        let e = _mm256_set_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY);
1400        assert_eq_m256d(r, e);
1401    }
1402
1403    #[simd_test(enable = "avx512f,avx512vl")]
1404    unsafe fn test_mm256_maskz_div_pd() {
1405        let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1406        let b = _mm256_set_pd(2., 2., 0., 0.);
1407        let r = _mm256_maskz_div_pd(0, a, b);
1408        assert_eq_m256d(r, _mm256_setzero_pd());
1409        let r = _mm256_maskz_div_pd(0b00001111, a, b);
1410        let e = _mm256_set_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY);
1411        assert_eq_m256d(r, e);
1412    }
1413
1414    #[simd_test(enable = "avx512f,avx512vl")]
1415    unsafe fn test_mm_mask_div_pd() {
1416        let a = _mm_set_pd(f64::MAX, f64::MIN);
1417        let b = _mm_set_pd(0., 0.);
1418        let r = _mm_mask_div_pd(a, 0, a, b);
1419        assert_eq_m128d(r, a);
1420        let r = _mm_mask_div_pd(a, 0b00000011, a, b);
1421        let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1422        assert_eq_m128d(r, e);
1423    }
1424
1425    #[simd_test(enable = "avx512f,avx512vl")]
1426    unsafe fn test_mm_maskz_div_pd() {
1427        let a = _mm_set_pd(f64::MAX, f64::MIN);
1428        let b = _mm_set_pd(0., 0.);
1429        let r = _mm_maskz_div_pd(0, a, b);
1430        assert_eq_m128d(r, _mm_setzero_pd());
1431        let r = _mm_maskz_div_pd(0b00000011, a, b);
1432        let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1433        assert_eq_m128d(r, e);
1434    }
1435
1436    #[simd_test(enable = "avx512f")]
1437    unsafe fn test_mm512_max_epi64() {
1438        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1439        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1440        let r = _mm512_max_epi64(a, b);
1441        let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1442        assert_eq_m512i(r, e);
1443    }
1444
1445    #[simd_test(enable = "avx512f")]
1446    unsafe fn test_mm512_mask_max_epi64() {
1447        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1448        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1449        let r = _mm512_mask_max_epi64(a, 0, a, b);
1450        assert_eq_m512i(r, a);
1451        let r = _mm512_mask_max_epi64(a, 0b00001111, a, b);
1452        let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1453        assert_eq_m512i(r, e);
1454    }
1455
1456    #[simd_test(enable = "avx512f")]
1457    unsafe fn test_mm512_maskz_max_epi64() {
1458        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1459        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1460        let r = _mm512_maskz_max_epi64(0, a, b);
1461        assert_eq_m512i(r, _mm512_setzero_si512());
1462        let r = _mm512_maskz_max_epi64(0b00001111, a, b);
1463        let e = _mm512_setr_epi64(7, 6, 5, 4, 0, 0, 0, 0);
1464        assert_eq_m512i(r, e);
1465    }
1466
1467    #[simd_test(enable = "avx512f,avx512vl")]
1468    unsafe fn test_mm256_max_epi64() {
1469        let a = _mm256_set_epi64x(0, 1, 2, 3);
1470        let b = _mm256_set_epi64x(3, 2, 1, 0);
1471        let r = _mm256_max_epi64(a, b);
1472        let e = _mm256_set_epi64x(3, 2, 2, 3);
1473        assert_eq_m256i(r, e);
1474    }
1475
1476    #[simd_test(enable = "avx512f,avx512vl")]
1477    unsafe fn test_mm256_mask_max_epi64() {
1478        let a = _mm256_set_epi64x(0, 1, 2, 3);
1479        let b = _mm256_set_epi64x(3, 2, 1, 0);
1480        let r = _mm256_mask_max_epi64(a, 0, a, b);
1481        assert_eq_m256i(r, a);
1482        let r = _mm256_mask_max_epi64(a, 0b00001111, a, b);
1483        let e = _mm256_set_epi64x(3, 2, 2, 3);
1484        assert_eq_m256i(r, e);
1485    }
1486
1487    #[simd_test(enable = "avx512f,avx512vl")]
1488    unsafe fn test_mm256_maskz_max_epi64() {
1489        let a = _mm256_set_epi64x(0, 1, 2, 3);
1490        let b = _mm256_set_epi64x(3, 2, 1, 0);
1491        let r = _mm256_maskz_max_epi64(0, a, b);
1492        assert_eq_m256i(r, _mm256_setzero_si256());
1493        let r = _mm256_maskz_max_epi64(0b00001111, a, b);
1494        let e = _mm256_set_epi64x(3, 2, 2, 3);
1495        assert_eq_m256i(r, e);
1496    }
1497
1498    #[simd_test(enable = "avx512f,avx512vl")]
1499    unsafe fn test_mm_max_epi64() {
1500        let a = _mm_set_epi64x(2, 3);
1501        let b = _mm_set_epi64x(3, 2);
1502        let r = _mm_max_epi64(a, b);
1503        let e = _mm_set_epi64x(3, 3);
1504        assert_eq_m128i(r, e);
1505    }
1506
1507    #[simd_test(enable = "avx512f,avx512vl")]
1508    unsafe fn test_mm_mask_max_epi64() {
1509        let a = _mm_set_epi64x(2, 3);
1510        let b = _mm_set_epi64x(3, 2);
1511        let r = _mm_mask_max_epi64(a, 0, a, b);
1512        assert_eq_m128i(r, a);
1513        let r = _mm_mask_max_epi64(a, 0b00000011, a, b);
1514        let e = _mm_set_epi64x(3, 3);
1515        assert_eq_m128i(r, e);
1516    }
1517
1518    #[simd_test(enable = "avx512f,avx512vl")]
1519    unsafe fn test_mm_maskz_max_epi64() {
1520        let a = _mm_set_epi64x(2, 3);
1521        let b = _mm_set_epi64x(3, 2);
1522        let r = _mm_maskz_max_epi64(0, a, b);
1523        assert_eq_m128i(r, _mm_setzero_si128());
1524        let r = _mm_maskz_max_epi64(0b00000011, a, b);
1525        let e = _mm_set_epi64x(3, 3);
1526        assert_eq_m128i(r, e);
1527    }
1528
1529    #[simd_test(enable = "avx512f")]
1530    unsafe fn test_mm512_max_pd() {
1531        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1532        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1533        let r = _mm512_max_pd(a, b);
1534        let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
1535        assert_eq_m512d(r, e);
1536    }
1537
1538    #[simd_test(enable = "avx512f")]
1539    unsafe fn test_mm512_mask_max_pd() {
1540        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1541        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1542        let r = _mm512_mask_max_pd(a, 0, a, b);
1543        assert_eq_m512d(r, a);
1544        let r = _mm512_mask_max_pd(a, 0b00001111, a, b);
1545        let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
1546        assert_eq_m512d(r, e);
1547    }
1548
1549    #[simd_test(enable = "avx512f")]
1550    unsafe fn test_mm512_maskz_max_pd() {
1551        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1552        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1553        let r = _mm512_maskz_max_pd(0, a, b);
1554        assert_eq_m512d(r, _mm512_setzero_pd());
1555        let r = _mm512_maskz_max_pd(0b00001111, a, b);
1556        let e = _mm512_setr_pd(7., 6., 5., 4., 0., 0., 0., 0.);
1557        assert_eq_m512d(r, e);
1558    }
1559
1560    #[simd_test(enable = "avx512f,avx512vl")]
1561    unsafe fn test_mm256_mask_max_pd() {
1562        let a = _mm256_set_pd(0., 1., 2., 3.);
1563        let b = _mm256_set_pd(3., 2., 1., 0.);
1564        let r = _mm256_mask_max_pd(a, 0, a, b);
1565        assert_eq_m256d(r, a);
1566        let r = _mm256_mask_max_pd(a, 0b00001111, a, b);
1567        let e = _mm256_set_pd(3., 2., 2., 3.);
1568        assert_eq_m256d(r, e);
1569    }
1570
1571    #[simd_test(enable = "avx512f,avx512vl")]
1572    unsafe fn test_mm256_maskz_max_pd() {
1573        let a = _mm256_set_pd(0., 1., 2., 3.);
1574        let b = _mm256_set_pd(3., 2., 1., 0.);
1575        let r = _mm256_maskz_max_pd(0, a, b);
1576        assert_eq_m256d(r, _mm256_setzero_pd());
1577        let r = _mm256_maskz_max_pd(0b00001111, a, b);
1578        let e = _mm256_set_pd(3., 2., 2., 3.);
1579        assert_eq_m256d(r, e);
1580    }
1581
1582    #[simd_test(enable = "avx512f,avx512vl")]
1583    unsafe fn test_mm_mask_max_pd() {
1584        let a = _mm_set_pd(2., 3.);
1585        let b = _mm_set_pd(3., 2.);
1586        let r = _mm_mask_max_pd(a, 0, a, b);
1587        assert_eq_m128d(r, a);
1588        let r = _mm_mask_max_pd(a, 0b00000011, a, b);
1589        let e = _mm_set_pd(3., 3.);
1590        assert_eq_m128d(r, e);
1591    }
1592
1593    #[simd_test(enable = "avx512f,avx512vl")]
1594    unsafe fn test_mm_maskz_max_pd() {
1595        let a = _mm_set_pd(2., 3.);
1596        let b = _mm_set_pd(3., 2.);
1597        let r = _mm_maskz_max_pd(0, a, b);
1598        assert_eq_m128d(r, _mm_setzero_pd());
1599        let r = _mm_maskz_max_pd(0b00000011, a, b);
1600        let e = _mm_set_pd(3., 3.);
1601        assert_eq_m128d(r, e);
1602    }
1603
1604    #[simd_test(enable = "avx512f")]
1605    unsafe fn test_mm512_max_epu64() {
1606        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1607        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1608        let r = _mm512_max_epu64(a, b);
1609        let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1610        assert_eq_m512i(r, e);
1611    }
1612
1613    #[simd_test(enable = "avx512f")]
1614    unsafe fn test_mm512_mask_max_epu64() {
1615        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1616        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1617        let r = _mm512_mask_max_epu64(a, 0, a, b);
1618        assert_eq_m512i(r, a);
1619        let r = _mm512_mask_max_epu64(a, 0b00001111, a, b);
1620        let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1621        assert_eq_m512i(r, e);
1622    }
1623
1624    #[simd_test(enable = "avx512f")]
1625    unsafe fn test_mm512_maskz_max_epu64() {
1626        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1627        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1628        let r = _mm512_maskz_max_epu64(0, a, b);
1629        assert_eq_m512i(r, _mm512_setzero_si512());
1630        let r = _mm512_maskz_max_epu64(0b00001111, a, b);
1631        let e = _mm512_setr_epi64(7, 6, 5, 4, 0, 0, 0, 0);
1632        assert_eq_m512i(r, e);
1633    }
1634
1635    #[simd_test(enable = "avx512f,avx512vl")]
1636    unsafe fn test_mm256_max_epu64() {
1637        let a = _mm256_set_epi64x(0, 1, 2, 3);
1638        let b = _mm256_set_epi64x(3, 2, 1, 0);
1639        let r = _mm256_max_epu64(a, b);
1640        let e = _mm256_set_epi64x(3, 2, 2, 3);
1641        assert_eq_m256i(r, e);
1642    }
1643
1644    #[simd_test(enable = "avx512f,avx512vl")]
1645    unsafe fn test_mm256_mask_max_epu64() {
1646        let a = _mm256_set_epi64x(0, 1, 2, 3);
1647        let b = _mm256_set_epi64x(3, 2, 1, 0);
1648        let r = _mm256_mask_max_epu64(a, 0, a, b);
1649        assert_eq_m256i(r, a);
1650        let r = _mm256_mask_max_epu64(a, 0b00001111, a, b);
1651        let e = _mm256_set_epi64x(3, 2, 2, 3);
1652        assert_eq_m256i(r, e);
1653    }
1654
1655    #[simd_test(enable = "avx512f,avx512vl")]
1656    unsafe fn test_mm256_maskz_max_epu64() {
1657        let a = _mm256_set_epi64x(0, 1, 2, 3);
1658        let b = _mm256_set_epi64x(3, 2, 1, 0);
1659        let r = _mm256_maskz_max_epu64(0, a, b);
1660        assert_eq_m256i(r, _mm256_setzero_si256());
1661        let r = _mm256_maskz_max_epu64(0b00001111, a, b);
1662        let e = _mm256_set_epi64x(3, 2, 2, 3);
1663        assert_eq_m256i(r, e);
1664    }
1665
1666    #[simd_test(enable = "avx512f,avx512vl")]
1667    unsafe fn test_mm_max_epu64() {
1668        let a = _mm_set_epi64x(2, 3);
1669        let b = _mm_set_epi64x(3, 2);
1670        let r = _mm_max_epu64(a, b);
1671        let e = _mm_set_epi64x(3, 3);
1672        assert_eq_m128i(r, e);
1673    }
1674
1675    #[simd_test(enable = "avx512f,avx512vl")]
1676    unsafe fn test_mm_mask_max_epu64() {
1677        let a = _mm_set_epi64x(2, 3);
1678        let b = _mm_set_epi64x(3, 2);
1679        let r = _mm_mask_max_epu64(a, 0, a, b);
1680        assert_eq_m128i(r, a);
1681        let r = _mm_mask_max_epu64(a, 0b00000011, a, b);
1682        let e = _mm_set_epi64x(3, 3);
1683        assert_eq_m128i(r, e);
1684    }
1685
1686    #[simd_test(enable = "avx512f,avx512vl")]
1687    unsafe fn test_mm_maskz_max_epu64() {
1688        let a = _mm_set_epi64x(2, 3);
1689        let b = _mm_set_epi64x(3, 2);
1690        let r = _mm_maskz_max_epu64(0, a, b);
1691        assert_eq_m128i(r, _mm_setzero_si128());
1692        let r = _mm_maskz_max_epu64(0b00000011, a, b);
1693        let e = _mm_set_epi64x(3, 3);
1694        assert_eq_m128i(r, e);
1695    }
1696
1697    #[simd_test(enable = "avx512f")]
1698    unsafe fn test_mm512_min_epi64() {
1699        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1700        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1701        let r = _mm512_min_epi64(a, b);
1702        let e = _mm512_setr_epi64(0, 1, 2, 3, 3, 2, 1, 0);
1703        assert_eq_m512i(r, e);
1704    }
1705
1706    #[simd_test(enable = "avx512f")]
1707    unsafe fn test_mm512_mask_min_epi64() {
1708        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1709        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1710        let r = _mm512_mask_min_epi64(a, 0, a, b);
1711        assert_eq_m512i(r, a);
1712        let r = _mm512_mask_min_epi64(a, 0b00001111, a, b);
1713        let e = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1714        assert_eq_m512i(r, e);
1715    }
1716
1717    #[simd_test(enable = "avx512f")]
1718    unsafe fn test_mm512_maskz_min_epi64() {
1719        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1720        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1721        let r = _mm512_maskz_min_epi64(0, a, b);
1722        assert_eq_m512i(r, _mm512_setzero_si512());
1723        let r = _mm512_maskz_min_epi64(0b00001111, a, b);
1724        let e = _mm512_setr_epi64(0, 1, 2, 3, 0, 0, 0, 0);
1725        assert_eq_m512i(r, e);
1726    }
1727
1728    #[simd_test(enable = "avx512f,avx512vl")]
1729    unsafe fn test_mm256_min_epi64() {
1730        let a = _mm256_set_epi64x(0, 1, 2, 3);
1731        let b = _mm256_set_epi64x(3, 2, 1, 0);
1732        let r = _mm256_min_epi64(a, b);
1733        let e = _mm256_set_epi64x(0, 1, 1, 0);
1734        assert_eq_m256i(r, e);
1735    }
1736
1737    #[simd_test(enable = "avx512f,avx512vl")]
1738    unsafe fn test_mm256_mask_min_epi64() {
1739        let a = _mm256_set_epi64x(0, 1, 2, 3);
1740        let b = _mm256_set_epi64x(3, 2, 1, 0);
1741        let r = _mm256_mask_min_epi64(a, 0, a, b);
1742        assert_eq_m256i(r, a);
1743        let r = _mm256_mask_min_epi64(a, 0b00001111, a, b);
1744        let e = _mm256_set_epi64x(0, 1, 1, 0);
1745        assert_eq_m256i(r, e);
1746    }
1747
1748    #[simd_test(enable = "avx512f,avx512vl")]
1749    unsafe fn test_mm256_maskz_min_epi64() {
1750        let a = _mm256_set_epi64x(0, 1, 2, 3);
1751        let b = _mm256_set_epi64x(3, 2, 1, 0);
1752        let r = _mm256_maskz_min_epi64(0, a, b);
1753        assert_eq_m256i(r, _mm256_setzero_si256());
1754        let r = _mm256_maskz_min_epi64(0b00001111, a, b);
1755        let e = _mm256_set_epi64x(0, 1, 1, 0);
1756        assert_eq_m256i(r, e);
1757    }
1758
1759    #[simd_test(enable = "avx512f,avx512vl")]
1760    unsafe fn test_mm_min_epi64() {
1761        let a = _mm_set_epi64x(0, 1);
1762        let b = _mm_set_epi64x(3, 2);
1763        let r = _mm_min_epi64(a, b);
1764        let e = _mm_set_epi64x(0, 1);
1765        assert_eq_m128i(r, e);
1766        let a = _mm_set_epi64x(2, 3);
1767        let b = _mm_set_epi64x(1, 0);
1768        let r = _mm_min_epi64(a, b);
1769        let e = _mm_set_epi64x(1, 0);
1770        assert_eq_m128i(r, e);
1771    }
1772
1773    #[simd_test(enable = "avx512f,avx512vl")]
1774    unsafe fn test_mm_mask_min_epi64() {
1775        let a = _mm_set_epi64x(0, 1);
1776        let b = _mm_set_epi64x(3, 2);
1777        let r = _mm_mask_min_epi64(a, 0, a, b);
1778        assert_eq_m128i(r, a);
1779        let r = _mm_mask_min_epi64(a, 0b00000011, a, b);
1780        let e = _mm_set_epi64x(0, 1);
1781        assert_eq_m128i(r, e);
1782    }
1783
1784    #[simd_test(enable = "avx512f,avx512vl")]
1785    unsafe fn test_mm_maskz_min_epi64() {
1786        let a = _mm_set_epi64x(0, 1);
1787        let b = _mm_set_epi64x(3, 2);
1788        let r = _mm_maskz_min_epi64(0, a, b);
1789        assert_eq_m128i(r, _mm_setzero_si128());
1790        let r = _mm_maskz_min_epi64(0b00000011, a, b);
1791        let e = _mm_set_epi64x(0, 1);
1792        assert_eq_m128i(r, e);
1793    }
1794
1795    #[simd_test(enable = "avx512f")]
1796    unsafe fn test_mm512_min_pd() {
1797        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1798        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1799        let r = _mm512_min_pd(a, b);
1800        let e = _mm512_setr_pd(0., 1., 2., 3., 3., 2., 1., 0.);
1801        assert_eq_m512d(r, e);
1802    }
1803
1804    #[simd_test(enable = "avx512f")]
1805    unsafe fn test_mm512_mask_min_pd() {
1806        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1807        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1808        let r = _mm512_mask_min_pd(a, 0, a, b);
1809        assert_eq_m512d(r, a);
1810        let r = _mm512_mask_min_pd(a, 0b00001111, a, b);
1811        let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1812        assert_eq_m512d(r, e);
1813    }
1814
1815    #[simd_test(enable = "avx512f")]
1816    unsafe fn test_mm512_maskz_min_pd() {
1817        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1818        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1819        let r = _mm512_maskz_min_pd(0, a, b);
1820        assert_eq_m512d(r, _mm512_setzero_pd());
1821        let r = _mm512_maskz_min_pd(0b00001111, a, b);
1822        let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
1823        assert_eq_m512d(r, e);
1824    }
1825
1826    #[simd_test(enable = "avx512f,avx512vl")]
1827    unsafe fn test_mm256_mask_min_pd() {
1828        let a = _mm256_set_pd(0., 1., 2., 3.);
1829        let b = _mm256_set_pd(3., 2., 1., 0.);
1830        let r = _mm256_mask_min_pd(a, 0, a, b);
1831        assert_eq_m256d(r, a);
1832        let r = _mm256_mask_min_pd(a, 0b00001111, a, b);
1833        let e = _mm256_set_pd(0., 1., 1., 0.);
1834        assert_eq_m256d(r, e);
1835    }
1836
1837    #[simd_test(enable = "avx512f,avx512vl")]
1838    unsafe fn test_mm256_maskz_min_pd() {
1839        let a = _mm256_set_pd(0., 1., 2., 3.);
1840        let b = _mm256_set_pd(3., 2., 1., 0.);
1841        let r = _mm256_maskz_min_pd(0, a, b);
1842        assert_eq_m256d(r, _mm256_setzero_pd());
1843        let r = _mm256_maskz_min_pd(0b00001111, a, b);
1844        let e = _mm256_set_pd(0., 1., 1., 0.);
1845        assert_eq_m256d(r, e);
1846    }
1847
1848    #[simd_test(enable = "avx512f,avx512vl")]
1849    unsafe fn test_mm_mask_min_pd() {
1850        let a = _mm_set_pd(0., 1.);
1851        let b = _mm_set_pd(1., 0.);
1852        let r = _mm_mask_min_pd(a, 0, a, b);
1853        assert_eq_m128d(r, a);
1854        let r = _mm_mask_min_pd(a, 0b00000011, a, b);
1855        let e = _mm_set_pd(0., 0.);
1856        assert_eq_m128d(r, e);
1857    }
1858
1859    #[simd_test(enable = "avx512f,avx512vl")]
1860    unsafe fn test_mm_maskz_min_pd() {
1861        let a = _mm_set_pd(0., 1.);
1862        let b = _mm_set_pd(1., 0.);
1863        let r = _mm_maskz_min_pd(0, a, b);
1864        assert_eq_m128d(r, _mm_setzero_pd());
1865        let r = _mm_maskz_min_pd(0b00000011, a, b);
1866        let e = _mm_set_pd(0., 0.);
1867        assert_eq_m128d(r, e);
1868    }
1869
1870    #[simd_test(enable = "avx512f")]
1871    unsafe fn test_mm512_min_epu64() {
1872        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1873        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1874        let r = _mm512_min_epu64(a, b);
1875        let e = _mm512_setr_epi64(0, 1, 2, 3, 3, 2, 1, 0);
1876        assert_eq_m512i(r, e);
1877    }
1878
1879    #[simd_test(enable = "avx512f")]
1880    unsafe fn test_mm512_mask_min_epu64() {
1881        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1882        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1883        let r = _mm512_mask_min_epu64(a, 0, a, b);
1884        assert_eq_m512i(r, a);
1885        let r = _mm512_mask_min_epu64(a, 0b00001111, a, b);
1886        let e = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1887        assert_eq_m512i(r, e);
1888    }
1889
1890    #[simd_test(enable = "avx512f")]
1891    unsafe fn test_mm512_maskz_min_epu64() {
1892        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1893        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1894        let r = _mm512_maskz_min_epu64(0, a, b);
1895        assert_eq_m512i(r, _mm512_setzero_si512());
1896        let r = _mm512_maskz_min_epu64(0b00001111, a, b);
1897        let e = _mm512_setr_epi64(0, 1, 2, 3, 0, 0, 0, 0);
1898        assert_eq_m512i(r, e);
1899    }
1900
1901    #[simd_test(enable = "avx512f,avx512vl")]
1902    unsafe fn test_mm256_min_epu64() {
1903        let a = _mm256_set_epi64x(0, 1, 2, 3);
1904        let b = _mm256_set_epi64x(3, 2, 1, 0);
1905        let r = _mm256_min_epu64(a, b);
1906        let e = _mm256_set_epi64x(0, 1, 1, 0);
1907        assert_eq_m256i(r, e);
1908    }
1909
1910    #[simd_test(enable = "avx512f,avx512vl")]
1911    unsafe fn test_mm256_mask_min_epu64() {
1912        let a = _mm256_set_epi64x(0, 1, 2, 3);
1913        let b = _mm256_set_epi64x(3, 2, 1, 0);
1914        let r = _mm256_mask_min_epu64(a, 0, a, b);
1915        assert_eq_m256i(r, a);
1916        let r = _mm256_mask_min_epu64(a, 0b00001111, a, b);
1917        let e = _mm256_set_epi64x(0, 1, 1, 0);
1918        assert_eq_m256i(r, e);
1919    }
1920
1921    #[simd_test(enable = "avx512f,avx512vl")]
1922    unsafe fn test_mm256_maskz_min_epu64() {
1923        let a = _mm256_set_epi64x(0, 1, 2, 3);
1924        let b = _mm256_set_epi64x(3, 2, 1, 0);
1925        let r = _mm256_maskz_min_epu64(0, a, b);
1926        assert_eq_m256i(r, _mm256_setzero_si256());
1927        let r = _mm256_maskz_min_epu64(0b00001111, a, b);
1928        let e = _mm256_set_epi64x(0, 1, 1, 0);
1929        assert_eq_m256i(r, e);
1930    }
1931
1932    #[simd_test(enable = "avx512f,avx512vl")]
1933    unsafe fn test_mm_min_epu64() {
1934        let a = _mm_set_epi64x(0, 1);
1935        let b = _mm_set_epi64x(1, 0);
1936        let r = _mm_min_epu64(a, b);
1937        let e = _mm_set_epi64x(0, 0);
1938        assert_eq_m128i(r, e);
1939    }
1940
1941    #[simd_test(enable = "avx512f,avx512vl")]
1942    unsafe fn test_mm_mask_min_epu64() {
1943        let a = _mm_set_epi64x(0, 1);
1944        let b = _mm_set_epi64x(1, 0);
1945        let r = _mm_mask_min_epu64(a, 0, a, b);
1946        assert_eq_m128i(r, a);
1947        let r = _mm_mask_min_epu64(a, 0b00000011, a, b);
1948        let e = _mm_set_epi64x(0, 0);
1949        assert_eq_m128i(r, e);
1950    }
1951
1952    #[simd_test(enable = "avx512f,avx512vl")]
1953    unsafe fn test_mm_maskz_min_epu64() {
1954        let a = _mm_set_epi64x(0, 1);
1955        let b = _mm_set_epi64x(1, 0);
1956        let r = _mm_maskz_min_epu64(0, a, b);
1957        assert_eq_m128i(r, _mm_setzero_si128());
1958        let r = _mm_maskz_min_epu64(0b00000011, a, b);
1959        let e = _mm_set_epi64x(0, 0);
1960        assert_eq_m128i(r, e);
1961    }
1962
1963    #[simd_test(enable = "avx512f")]
1964    unsafe fn test_mm512_sqrt_pd() {
1965        let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1966        let r = _mm512_sqrt_pd(a);
1967        let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1968        assert_eq_m512d(r, e);
1969    }
1970
1971    #[simd_test(enable = "avx512f")]
1972    unsafe fn test_mm512_mask_sqrt_pd() {
1973        let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1974        let r = _mm512_mask_sqrt_pd(a, 0, a);
1975        assert_eq_m512d(r, a);
1976        let r = _mm512_mask_sqrt_pd(a, 0b00001111, a);
1977        let e = _mm512_setr_pd(0., 1., 2., 3., 16., 25., 36., 49.);
1978        assert_eq_m512d(r, e);
1979    }
1980
1981    #[simd_test(enable = "avx512f")]
1982    unsafe fn test_mm512_maskz_sqrt_pd() {
1983        let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1984        let r = _mm512_maskz_sqrt_pd(0, a);
1985        assert_eq_m512d(r, _mm512_setzero_pd());
1986        let r = _mm512_maskz_sqrt_pd(0b00001111, a);
1987        let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
1988        assert_eq_m512d(r, e);
1989    }
1990
1991    #[simd_test(enable = "avx512f,avx512vl")]
1992    unsafe fn test_mm256_mask_sqrt_pd() {
1993        let a = _mm256_set_pd(0., 1., 4., 9.);
1994        let r = _mm256_mask_sqrt_pd(a, 0, a);
1995        assert_eq_m256d(r, a);
1996        let r = _mm256_mask_sqrt_pd(a, 0b00001111, a);
1997        let e = _mm256_set_pd(0., 1., 2., 3.);
1998        assert_eq_m256d(r, e);
1999    }
2000
2001    #[simd_test(enable = "avx512f,avx512vl")]
2002    unsafe fn test_mm256_maskz_sqrt_pd() {
2003        let a = _mm256_set_pd(0., 1., 4., 9.);
2004        let r = _mm256_maskz_sqrt_pd(0, a);
2005        assert_eq_m256d(r, _mm256_setzero_pd());
2006        let r = _mm256_maskz_sqrt_pd(0b00001111, a);
2007        let e = _mm256_set_pd(0., 1., 2., 3.);
2008        assert_eq_m256d(r, e);
2009    }
2010
2011    #[simd_test(enable = "avx512f,avx512vl")]
2012    unsafe fn test_mm_mask_sqrt_pd() {
2013        let a = _mm_set_pd(0., 1.);
2014        let r = _mm_mask_sqrt_pd(a, 0, a);
2015        assert_eq_m128d(r, a);
2016        let r = _mm_mask_sqrt_pd(a, 0b00000011, a);
2017        let e = _mm_set_pd(0., 1.);
2018        assert_eq_m128d(r, e);
2019    }
2020
2021    #[simd_test(enable = "avx512f,avx512vl")]
2022    unsafe fn test_mm_maskz_sqrt_pd() {
2023        let a = _mm_set_pd(0., 1.);
2024        let r = _mm_maskz_sqrt_pd(0, a);
2025        assert_eq_m128d(r, _mm_setzero_pd());
2026        let r = _mm_maskz_sqrt_pd(0b00000011, a);
2027        let e = _mm_set_pd(0., 1.);
2028        assert_eq_m128d(r, e);
2029    }
2030
2031    #[simd_test(enable = "avx512f")]
2032    unsafe fn test_mm512_fmadd_pd() {
2033        let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2034        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2035        let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2036        let r = _mm512_fmadd_pd(a, b, c);
2037        let e = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
2038        assert_eq_m512d(r, e);
2039    }
2040
2041    #[simd_test(enable = "avx512f")]
2042    unsafe fn test_mm512_mask_fmadd_pd() {
2043        let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2044        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2045        let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2046        let r = _mm512_mask_fmadd_pd(a, 0, b, c);
2047        assert_eq_m512d(r, a);
2048        let r = _mm512_mask_fmadd_pd(a, 0b00001111, b, c);
2049        let e = _mm512_setr_pd(1., 2., 3., 4., 1., 1., 1., 1.);
2050        assert_eq_m512d(r, e);
2051    }
2052
2053    #[simd_test(enable = "avx512f")]
2054    unsafe fn test_mm512_maskz_fmadd_pd() {
2055        let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2056        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2057        let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2058        let r = _mm512_maskz_fmadd_pd(0, a, b, c);
2059        assert_eq_m512d(r, _mm512_setzero_pd());
2060        let r = _mm512_maskz_fmadd_pd(0b00001111, a, b, c);
2061        let e = _mm512_setr_pd(1., 2., 3., 4., 0., 0., 0., 0.);
2062        assert_eq_m512d(r, e);
2063    }
2064
2065    #[simd_test(enable = "avx512f")]
2066    unsafe fn test_mm512_mask3_fmadd_pd() {
2067        let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2068        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2069        let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2070        let r = _mm512_mask3_fmadd_pd(a, b, c, 0);
2071        assert_eq_m512d(r, c);
2072        let r = _mm512_mask3_fmadd_pd(a, b, c, 0b00001111);
2073        let e = _mm512_setr_pd(1., 2., 3., 4., 2., 2., 2., 2.);
2074        assert_eq_m512d(r, e);
2075    }
2076
2077    #[simd_test(enable = "avx512f,avx512vl")]
2078    unsafe fn test_mm256_mask_fmadd_pd() {
2079        let a = _mm256_set1_pd(1.);
2080        let b = _mm256_set_pd(0., 1., 2., 3.);
2081        let c = _mm256_set1_pd(1.);
2082        let r = _mm256_mask_fmadd_pd(a, 0, b, c);
2083        assert_eq_m256d(r, a);
2084        let r = _mm256_mask_fmadd_pd(a, 0b00001111, b, c);
2085        let e = _mm256_set_pd(1., 2., 3., 4.);
2086        assert_eq_m256d(r, e);
2087    }
2088
2089    #[simd_test(enable = "avx512f,avx512vl")]
2090    unsafe fn test_mm256_maskz_fmadd_pd() {
2091        let a = _mm256_set1_pd(1.);
2092        let b = _mm256_set_pd(0., 1., 2., 3.);
2093        let c = _mm256_set1_pd(1.);
2094        let r = _mm256_maskz_fmadd_pd(0, a, b, c);
2095        assert_eq_m256d(r, _mm256_setzero_pd());
2096        let r = _mm256_maskz_fmadd_pd(0b00001111, a, b, c);
2097        let e = _mm256_set_pd(1., 2., 3., 4.);
2098        assert_eq_m256d(r, e);
2099    }
2100
2101    #[simd_test(enable = "avx512f,avx512vl")]
2102    unsafe fn test_mm256_mask3_fmadd_pd() {
2103        let a = _mm256_set1_pd(1.);
2104        let b = _mm256_set_pd(0., 1., 2., 3.);
2105        let c = _mm256_set1_pd(1.);
2106        let r = _mm256_mask3_fmadd_pd(a, b, c, 0);
2107        assert_eq_m256d(r, c);
2108        let r = _mm256_mask3_fmadd_pd(a, b, c, 0b00001111);
2109        let e = _mm256_set_pd(1., 2., 3., 4.);
2110        assert_eq_m256d(r, e);
2111    }
2112
2113    #[simd_test(enable = "avx512f,avx512vl")]
2114    unsafe fn test_mm_mask_fmadd_pd() {
2115        let a = _mm_set1_pd(1.);
2116        let b = _mm_set_pd(0., 1.);
2117        let c = _mm_set1_pd(1.);
2118        let r = _mm_mask_fmadd_pd(a, 0, b, c);
2119        assert_eq_m128d(r, a);
2120        let r = _mm_mask_fmadd_pd(a, 0b00000011, b, c);
2121        let e = _mm_set_pd(1., 2.);
2122        assert_eq_m128d(r, e);
2123    }
2124
2125    #[simd_test(enable = "avx512f,avx512vl")]
2126    unsafe fn test_mm_maskz_fmadd_pd() {
2127        let a = _mm_set1_pd(1.);
2128        let b = _mm_set_pd(0., 1.);
2129        let c = _mm_set1_pd(1.);
2130        let r = _mm_maskz_fmadd_pd(0, a, b, c);
2131        assert_eq_m128d(r, _mm_setzero_pd());
2132        let r = _mm_maskz_fmadd_pd(0b00000011, a, b, c);
2133        let e = _mm_set_pd(1., 2.);
2134        assert_eq_m128d(r, e);
2135    }
2136
2137    #[simd_test(enable = "avx512f,avx512vl")]
2138    unsafe fn test_mm_mask3_fmadd_pd() {
2139        let a = _mm_set1_pd(1.);
2140        let b = _mm_set_pd(0., 1.);
2141        let c = _mm_set1_pd(1.);
2142        let r = _mm_mask3_fmadd_pd(a, b, c, 0);
2143        assert_eq_m128d(r, c);
2144        let r = _mm_mask3_fmadd_pd(a, b, c, 0b00000011);
2145        let e = _mm_set_pd(1., 2.);
2146        assert_eq_m128d(r, e);
2147    }
2148
2149    #[simd_test(enable = "avx512f")]
2150    unsafe fn test_mm512_fmsub_pd() {
2151        let a = _mm512_set1_pd(1.);
2152        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2153        let c = _mm512_set1_pd(1.);
2154        let r = _mm512_fmsub_pd(a, b, c);
2155        let e = _mm512_setr_pd(-1., 0., 1., 2., 3., 4., 5., 6.);
2156        assert_eq_m512d(r, e);
2157    }
2158
2159    #[simd_test(enable = "avx512f")]
2160    unsafe fn test_mm512_mask_fmsub_pd() {
2161        let a = _mm512_set1_pd(1.);
2162        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2163        let c = _mm512_set1_pd(1.);
2164        let r = _mm512_mask_fmsub_pd(a, 0, b, c);
2165        assert_eq_m512d(r, a);
2166        let r = _mm512_mask_fmsub_pd(a, 0b00001111, b, c);
2167        let e = _mm512_setr_pd(-1., 0., 1., 2., 1., 1., 1., 1.);
2168        assert_eq_m512d(r, e);
2169    }
2170
2171    #[simd_test(enable = "avx512f")]
2172    unsafe fn test_mm512_maskz_fmsub_pd() {
2173        let a = _mm512_set1_pd(1.);
2174        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2175        let c = _mm512_set1_pd(1.);
2176        let r = _mm512_maskz_fmsub_pd(0, a, b, c);
2177        assert_eq_m512d(r, _mm512_setzero_pd());
2178        let r = _mm512_maskz_fmsub_pd(0b00001111, a, b, c);
2179        let e = _mm512_setr_pd(-1., 0., 1., 2., 0., 0., 0., 0.);
2180        assert_eq_m512d(r, e);
2181    }
2182
2183    #[simd_test(enable = "avx512f")]
2184    unsafe fn test_mm512_mask3_fmsub_pd() {
2185        let a = _mm512_set1_pd(1.);
2186        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2187        let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2188        let r = _mm512_mask3_fmsub_pd(a, b, c, 0);
2189        assert_eq_m512d(r, c);
2190        let r = _mm512_mask3_fmsub_pd(a, b, c, 0b00001111);
2191        let e = _mm512_setr_pd(-1., 0., 1., 2., 2., 2., 2., 2.);
2192        assert_eq_m512d(r, e);
2193    }
2194
2195    #[simd_test(enable = "avx512f,avx512vl")]
2196    unsafe fn test_mm256_mask_fmsub_pd() {
2197        let a = _mm256_set1_pd(1.);
2198        let b = _mm256_set_pd(0., 1., 2., 3.);
2199        let c = _mm256_set1_pd(1.);
2200        let r = _mm256_mask_fmsub_pd(a, 0, b, c);
2201        assert_eq_m256d(r, a);
2202        let r = _mm256_mask_fmsub_pd(a, 0b00001111, b, c);
2203        let e = _mm256_set_pd(-1., 0., 1., 2.);
2204        assert_eq_m256d(r, e);
2205    }
2206
2207    #[simd_test(enable = "avx512f,avx512vl")]
2208    unsafe fn test_mm256_maskz_fmsub_pd() {
2209        let a = _mm256_set1_pd(1.);
2210        let b = _mm256_set_pd(0., 1., 2., 3.);
2211        let c = _mm256_set1_pd(1.);
2212        let r = _mm256_maskz_fmsub_pd(0, a, b, c);
2213        assert_eq_m256d(r, _mm256_setzero_pd());
2214        let r = _mm256_maskz_fmsub_pd(0b00001111, a, b, c);
2215        let e = _mm256_set_pd(-1., 0., 1., 2.);
2216        assert_eq_m256d(r, e);
2217    }
2218
2219    #[simd_test(enable = "avx512f,avx512vl")]
2220    unsafe fn test_mm256_mask3_fmsub_pd() {
2221        let a = _mm256_set1_pd(1.);
2222        let b = _mm256_set_pd(0., 1., 2., 3.);
2223        let c = _mm256_set1_pd(1.);
2224        let r = _mm256_mask3_fmsub_pd(a, b, c, 0);
2225        assert_eq_m256d(r, c);
2226        let r = _mm256_mask3_fmsub_pd(a, b, c, 0b00001111);
2227        let e = _mm256_set_pd(-1., 0., 1., 2.);
2228        assert_eq_m256d(r, e);
2229    }
2230
2231    #[simd_test(enable = "avx512f,avx512vl")]
2232    unsafe fn test_mm_mask_fmsub_pd() {
2233        let a = _mm_set1_pd(1.);
2234        let b = _mm_set_pd(0., 1.);
2235        let c = _mm_set1_pd(1.);
2236        let r = _mm_mask_fmsub_pd(a, 0, b, c);
2237        assert_eq_m128d(r, a);
2238        let r = _mm_mask_fmsub_pd(a, 0b00000011, b, c);
2239        let e = _mm_set_pd(-1., 0.);
2240        assert_eq_m128d(r, e);
2241    }
2242
2243    #[simd_test(enable = "avx512f,avx512vl")]
2244    unsafe fn test_mm_maskz_fmsub_pd() {
2245        let a = _mm_set1_pd(1.);
2246        let b = _mm_set_pd(0., 1.);
2247        let c = _mm_set1_pd(1.);
2248        let r = _mm_maskz_fmsub_pd(0, a, b, c);
2249        assert_eq_m128d(r, _mm_setzero_pd());
2250        let r = _mm_maskz_fmsub_pd(0b00000011, a, b, c);
2251        let e = _mm_set_pd(-1., 0.);
2252        assert_eq_m128d(r, e);
2253    }
2254
2255    #[simd_test(enable = "avx512f,avx512vl")]
2256    unsafe fn test_mm_mask3_fmsub_pd() {
2257        let a = _mm_set1_pd(1.);
2258        let b = _mm_set_pd(0., 1.);
2259        let c = _mm_set1_pd(1.);
2260        let r = _mm_mask3_fmsub_pd(a, b, c, 0);
2261        assert_eq_m128d(r, c);
2262        let r = _mm_mask3_fmsub_pd(a, b, c, 0b00000011);
2263        let e = _mm_set_pd(-1., 0.);
2264        assert_eq_m128d(r, e);
2265    }
2266
2267    #[simd_test(enable = "avx512f")]
2268    unsafe fn test_mm512_fmaddsub_pd() {
2269        let a = _mm512_set1_pd(1.);
2270        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2271        let c = _mm512_set1_pd(1.);
2272        let r = _mm512_fmaddsub_pd(a, b, c);
2273        let e = _mm512_setr_pd(-1., 2., 1., 4., 3., 6., 5., 8.);
2274        assert_eq_m512d(r, e);
2275    }
2276
2277    #[simd_test(enable = "avx512f")]
2278    unsafe fn test_mm512_mask_fmaddsub_pd() {
2279        let a = _mm512_set1_pd(1.);
2280        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2281        let c = _mm512_set1_pd(1.);
2282        let r = _mm512_mask_fmaddsub_pd(a, 0, b, c);
2283        assert_eq_m512d(r, a);
2284        let r = _mm512_mask_fmaddsub_pd(a, 0b00001111, b, c);
2285        let e = _mm512_setr_pd(-1., 2., 1., 4., 1., 1., 1., 1.);
2286        assert_eq_m512d(r, e);
2287    }
2288
2289    #[simd_test(enable = "avx512f")]
2290    unsafe fn test_mm512_maskz_fmaddsub_pd() {
2291        let a = _mm512_set1_pd(1.);
2292        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2293        let c = _mm512_set1_pd(1.);
2294        let r = _mm512_maskz_fmaddsub_pd(0, a, b, c);
2295        assert_eq_m512d(r, _mm512_setzero_pd());
2296        let r = _mm512_maskz_fmaddsub_pd(0b00001111, a, b, c);
2297        let e = _mm512_setr_pd(-1., 2., 1., 4., 0., 0., 0., 0.);
2298        assert_eq_m512d(r, e);
2299    }
2300
2301    #[simd_test(enable = "avx512f")]
2302    unsafe fn test_mm512_mask3_fmaddsub_pd() {
2303        let a = _mm512_set1_pd(1.);
2304        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2305        let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2306        let r = _mm512_mask3_fmaddsub_pd(a, b, c, 0);
2307        assert_eq_m512d(r, c);
2308        let r = _mm512_mask3_fmaddsub_pd(a, b, c, 0b00001111);
2309        let e = _mm512_setr_pd(-1., 2., 1., 4., 2., 2., 2., 2.);
2310        assert_eq_m512d(r, e);
2311    }
2312
2313    #[simd_test(enable = "avx512f,avx512vl")]
2314    unsafe fn test_mm256_mask_fmaddsub_pd() {
2315        let a = _mm256_set1_pd(1.);
2316        let b = _mm256_set_pd(0., 1., 2., 3.);
2317        let c = _mm256_set1_pd(1.);
2318        let r = _mm256_mask_fmaddsub_pd(a, 0, b, c);
2319        assert_eq_m256d(r, a);
2320        let r = _mm256_mask_fmaddsub_pd(a, 0b00001111, b, c);
2321        let e = _mm256_set_pd(1., 0., 3., 2.);
2322        assert_eq_m256d(r, e);
2323    }
2324
2325    #[simd_test(enable = "avx512f,avx512vl")]
2326    unsafe fn test_mm256_maskz_fmaddsub_pd() {
2327        let a = _mm256_set1_pd(1.);
2328        let b = _mm256_set_pd(0., 1., 2., 3.);
2329        let c = _mm256_set1_pd(1.);
2330        let r = _mm256_maskz_fmaddsub_pd(0, a, b, c);
2331        assert_eq_m256d(r, _mm256_setzero_pd());
2332        let r = _mm256_maskz_fmaddsub_pd(0b00001111, a, b, c);
2333        let e = _mm256_set_pd(1., 0., 3., 2.);
2334        assert_eq_m256d(r, e);
2335    }
2336
2337    #[simd_test(enable = "avx512f,avx512vl")]
2338    unsafe fn test_mm256_mask3_fmaddsub_pd() {
2339        let a = _mm256_set1_pd(1.);
2340        let b = _mm256_set_pd(0., 1., 2., 3.);
2341        let c = _mm256_set1_pd(1.);
2342        let r = _mm256_mask3_fmaddsub_pd(a, b, c, 0);
2343        assert_eq_m256d(r, c);
2344        let r = _mm256_mask3_fmaddsub_pd(a, b, c, 0b00001111);
2345        let e = _mm256_set_pd(1., 0., 3., 2.);
2346        assert_eq_m256d(r, e);
2347    }
2348
2349    #[simd_test(enable = "avx512f,avx512vl")]
2350    unsafe fn test_mm_mask_fmaddsub_pd() {
2351        let a = _mm_set1_pd(1.);
2352        let b = _mm_set_pd(0., 1.);
2353        let c = _mm_set1_pd(1.);
2354        let r = _mm_mask_fmaddsub_pd(a, 0, b, c);
2355        assert_eq_m128d(r, a);
2356        let r = _mm_mask_fmaddsub_pd(a, 0b00000011, b, c);
2357        let e = _mm_set_pd(1., 0.);
2358        assert_eq_m128d(r, e);
2359    }
2360
2361    #[simd_test(enable = "avx512f,avx512vl")]
2362    unsafe fn test_mm_maskz_fmaddsub_pd() {
2363        let a = _mm_set1_pd(1.);
2364        let b = _mm_set_pd(0., 1.);
2365        let c = _mm_set1_pd(1.);
2366        let r = _mm_maskz_fmaddsub_pd(0, a, b, c);
2367        assert_eq_m128d(r, _mm_setzero_pd());
2368        let r = _mm_maskz_fmaddsub_pd(0b00000011, a, b, c);
2369        let e = _mm_set_pd(1., 0.);
2370        assert_eq_m128d(r, e);
2371    }
2372
2373    #[simd_test(enable = "avx512f,avx512vl")]
2374    unsafe fn test_mm_mask3_fmaddsub_pd() {
2375        let a = _mm_set1_pd(1.);
2376        let b = _mm_set_pd(0., 1.);
2377        let c = _mm_set1_pd(1.);
2378        let r = _mm_mask3_fmaddsub_pd(a, b, c, 0);
2379        assert_eq_m128d(r, c);
2380        let r = _mm_mask3_fmaddsub_pd(a, b, c, 0b00000011);
2381        let e = _mm_set_pd(1., 0.);
2382        assert_eq_m128d(r, e);
2383    }
2384
2385    #[simd_test(enable = "avx512f")]
2386    unsafe fn test_mm512_fmsubadd_pd() {
2387        let a = _mm512_set1_pd(1.);
2388        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2389        let c = _mm512_set1_pd(1.);
2390        let r = _mm512_fmsubadd_pd(a, b, c);
2391        let e = _mm512_setr_pd(1., 0., 3., 2., 5., 4., 7., 6.);
2392        assert_eq_m512d(r, e);
2393    }
2394
2395    #[simd_test(enable = "avx512f")]
2396    unsafe fn test_mm512_mask_fmsubadd_pd() {
2397        let a = _mm512_set1_pd(1.);
2398        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2399        let c = _mm512_set1_pd(1.);
2400        let r = _mm512_mask_fmsubadd_pd(a, 0, b, c);
2401        assert_eq_m512d(r, a);
2402        let r = _mm512_mask_fmsubadd_pd(a, 0b00001111, b, c);
2403        let e = _mm512_setr_pd(1., 0., 3., 2., 1., 1., 1., 1.);
2404        assert_eq_m512d(r, e);
2405    }
2406
2407    #[simd_test(enable = "avx512f")]
2408    unsafe fn test_mm512_maskz_fmsubadd_pd() {
2409        let a = _mm512_set1_pd(1.);
2410        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2411        let c = _mm512_set1_pd(1.);
2412        let r = _mm512_maskz_fmsubadd_pd(0, a, b, c);
2413        assert_eq_m512d(r, _mm512_setzero_pd());
2414        let r = _mm512_maskz_fmsubadd_pd(0b00001111, a, b, c);
2415        let e = _mm512_setr_pd(1., 0., 3., 2., 0., 0., 0., 0.);
2416        assert_eq_m512d(r, e);
2417    }
2418
2419    #[simd_test(enable = "avx512f")]
2420    unsafe fn test_mm512_mask3_fmsubadd_pd() {
2421        let a = _mm512_set1_pd(1.);
2422        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2423        let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2424        let r = _mm512_mask3_fmsubadd_pd(a, b, c, 0);
2425        assert_eq_m512d(r, c);
2426        let r = _mm512_mask3_fmsubadd_pd(a, b, c, 0b00001111);
2427        let e = _mm512_setr_pd(1., 0., 3., 2., 2., 2., 2., 2.);
2428        assert_eq_m512d(r, e);
2429    }
2430
2431    #[simd_test(enable = "avx512f,avx512vl")]
2432    unsafe fn test_mm256_mask_fmsubadd_pd() {
2433        let a = _mm256_set1_pd(1.);
2434        let b = _mm256_set_pd(0., 1., 2., 3.);
2435        let c = _mm256_set1_pd(1.);
2436        let r = _mm256_mask_fmsubadd_pd(a, 0, b, c);
2437        assert_eq_m256d(r, a);
2438        let r = _mm256_mask_fmsubadd_pd(a, 0b00001111, b, c);
2439        let e = _mm256_set_pd(-1., 2., 1., 4.);
2440        assert_eq_m256d(r, e);
2441    }
2442
2443    #[simd_test(enable = "avx512f,avx512vl")]
2444    unsafe fn test_mm256_maskz_fmsubadd_pd() {
2445        let a = _mm256_set1_pd(1.);
2446        let b = _mm256_set_pd(0., 1., 2., 3.);
2447        let c = _mm256_set1_pd(1.);
2448        let r = _mm256_maskz_fmsubadd_pd(0, a, b, c);
2449        assert_eq_m256d(r, _mm256_setzero_pd());
2450        let r = _mm256_maskz_fmsubadd_pd(0b00001111, a, b, c);
2451        let e = _mm256_set_pd(-1., 2., 1., 4.);
2452        assert_eq_m256d(r, e);
2453    }
2454
2455    #[simd_test(enable = "avx512f,avx512vl")]
2456    unsafe fn test_mm256_mask3_fmsubadd_pd() {
2457        let a = _mm256_set1_pd(1.);
2458        let b = _mm256_set_pd(0., 1., 2., 3.);
2459        let c = _mm256_set1_pd(1.);
2460        let r = _mm256_mask3_fmsubadd_pd(a, b, c, 0);
2461        assert_eq_m256d(r, c);
2462        let r = _mm256_mask3_fmsubadd_pd(a, b, c, 0b00001111);
2463        let e = _mm256_set_pd(-1., 2., 1., 4.);
2464        assert_eq_m256d(r, e);
2465    }
2466
2467    #[simd_test(enable = "avx512f,avx512vl")]
2468    unsafe fn test_mm_mask_fmsubadd_pd() {
2469        let a = _mm_set1_pd(1.);
2470        let b = _mm_set_pd(0., 1.);
2471        let c = _mm_set1_pd(1.);
2472        let r = _mm_mask_fmsubadd_pd(a, 0, b, c);
2473        assert_eq_m128d(r, a);
2474        let r = _mm_mask_fmsubadd_pd(a, 0b00000011, b, c);
2475        let e = _mm_set_pd(-1., 2.);
2476        assert_eq_m128d(r, e);
2477    }
2478
2479    #[simd_test(enable = "avx512f,avx512vl")]
2480    unsafe fn test_mm_maskz_fmsubadd_pd() {
2481        let a = _mm_set1_pd(1.);
2482        let b = _mm_set_pd(0., 1.);
2483        let c = _mm_set1_pd(1.);
2484        let r = _mm_maskz_fmsubadd_pd(0, a, b, c);
2485        assert_eq_m128d(r, _mm_setzero_pd());
2486        let r = _mm_maskz_fmsubadd_pd(0b00000011, a, b, c);
2487        let e = _mm_set_pd(-1., 2.);
2488        assert_eq_m128d(r, e);
2489    }
2490
2491    #[simd_test(enable = "avx512f,avx512vl")]
2492    unsafe fn test_mm_mask3_fmsubadd_pd() {
2493        let a = _mm_set1_pd(1.);
2494        let b = _mm_set_pd(0., 1.);
2495        let c = _mm_set1_pd(1.);
2496        let r = _mm_mask3_fmsubadd_pd(a, b, c, 0);
2497        assert_eq_m128d(r, c);
2498        let r = _mm_mask3_fmsubadd_pd(a, b, c, 0b00000011);
2499        let e = _mm_set_pd(-1., 2.);
2500        assert_eq_m128d(r, e);
2501    }
2502
2503    #[simd_test(enable = "avx512f")]
2504    unsafe fn test_mm512_fnmadd_pd() {
2505        let a = _mm512_set1_pd(1.);
2506        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2507        let c = _mm512_set1_pd(1.);
2508        let r = _mm512_fnmadd_pd(a, b, c);
2509        let e = _mm512_setr_pd(1., 0., -1., -2., -3., -4., -5., -6.);
2510        assert_eq_m512d(r, e);
2511    }
2512
2513    #[simd_test(enable = "avx512f")]
2514    unsafe fn test_mm512_mask_fnmadd_pd() {
2515        let a = _mm512_set1_pd(1.);
2516        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2517        let c = _mm512_set1_pd(1.);
2518        let r = _mm512_mask_fnmadd_pd(a, 0, b, c);
2519        assert_eq_m512d(r, a);
2520        let r = _mm512_mask_fnmadd_pd(a, 0b00001111, b, c);
2521        let e = _mm512_setr_pd(1., 0., -1., -2., 1., 1., 1., 1.);
2522        assert_eq_m512d(r, e);
2523    }
2524
2525    #[simd_test(enable = "avx512f")]
2526    unsafe fn test_mm512_maskz_fnmadd_pd() {
2527        let a = _mm512_set1_pd(1.);
2528        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2529        let c = _mm512_set1_pd(1.);
2530        let r = _mm512_maskz_fnmadd_pd(0, a, b, c);
2531        assert_eq_m512d(r, _mm512_setzero_pd());
2532        let r = _mm512_maskz_fnmadd_pd(0b00001111, a, b, c);
2533        let e = _mm512_setr_pd(1., 0., -1., -2., 0., 0., 0., 0.);
2534        assert_eq_m512d(r, e);
2535    }
2536
2537    #[simd_test(enable = "avx512f")]
2538    unsafe fn test_mm512_mask3_fnmadd_pd() {
2539        let a = _mm512_set1_pd(1.);
2540        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2541        let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2542        let r = _mm512_mask3_fnmadd_pd(a, b, c, 0);
2543        assert_eq_m512d(r, c);
2544        let r = _mm512_mask3_fnmadd_pd(a, b, c, 0b00001111);
2545        let e = _mm512_setr_pd(1., 0., -1., -2., 2., 2., 2., 2.);
2546        assert_eq_m512d(r, e);
2547    }
2548
2549    #[simd_test(enable = "avx512f,avx512vl")]
2550    unsafe fn test_mm256_mask_fnmadd_pd() {
2551        let a = _mm256_set1_pd(1.);
2552        let b = _mm256_set_pd(0., 1., 2., 3.);
2553        let c = _mm256_set1_pd(1.);
2554        let r = _mm256_mask_fnmadd_pd(a, 0, b, c);
2555        assert_eq_m256d(r, a);
2556        let r = _mm256_mask_fnmadd_pd(a, 0b00001111, b, c);
2557        let e = _mm256_set_pd(1., 0., -1., -2.);
2558        assert_eq_m256d(r, e);
2559    }
2560
2561    #[simd_test(enable = "avx512f,avx512vl")]
2562    unsafe fn test_mm256_maskz_fnmadd_pd() {
2563        let a = _mm256_set1_pd(1.);
2564        let b = _mm256_set_pd(0., 1., 2., 3.);
2565        let c = _mm256_set1_pd(1.);
2566        let r = _mm256_maskz_fnmadd_pd(0, a, b, c);
2567        assert_eq_m256d(r, _mm256_setzero_pd());
2568        let r = _mm256_maskz_fnmadd_pd(0b00001111, a, b, c);
2569        let e = _mm256_set_pd(1., 0., -1., -2.);
2570        assert_eq_m256d(r, e);
2571    }
2572
2573    #[simd_test(enable = "avx512f,avx512vl")]
2574    unsafe fn test_mm256_mask3_fnmadd_pd() {
2575        let a = _mm256_set1_pd(1.);
2576        let b = _mm256_set_pd(0., 1., 2., 3.);
2577        let c = _mm256_set1_pd(1.);
2578        let r = _mm256_mask3_fnmadd_pd(a, b, c, 0);
2579        assert_eq_m256d(r, c);
2580        let r = _mm256_mask3_fnmadd_pd(a, b, c, 0b00001111);
2581        let e = _mm256_set_pd(1., 0., -1., -2.);
2582        assert_eq_m256d(r, e);
2583    }
2584
2585    #[simd_test(enable = "avx512f,avx512vl")]
2586    unsafe fn test_mm_mask_fnmadd_pd() {
2587        let a = _mm_set1_pd(1.);
2588        let b = _mm_set_pd(0., 1.);
2589        let c = _mm_set1_pd(1.);
2590        let r = _mm_mask_fnmadd_pd(a, 0, b, c);
2591        assert_eq_m128d(r, a);
2592        let r = _mm_mask_fnmadd_pd(a, 0b00000011, b, c);
2593        let e = _mm_set_pd(1., 0.);
2594        assert_eq_m128d(r, e);
2595    }
2596
2597    #[simd_test(enable = "avx512f,avx512vl")]
2598    unsafe fn test_mm_maskz_fnmadd_pd() {
2599        let a = _mm_set1_pd(1.);
2600        let b = _mm_set_pd(0., 1.);
2601        let c = _mm_set1_pd(1.);
2602        let r = _mm_maskz_fnmadd_pd(0, a, b, c);
2603        assert_eq_m128d(r, _mm_setzero_pd());
2604        let r = _mm_maskz_fnmadd_pd(0b00000011, a, b, c);
2605        let e = _mm_set_pd(1., 0.);
2606        assert_eq_m128d(r, e);
2607    }
2608
2609    #[simd_test(enable = "avx512f,avx512vl")]
2610    unsafe fn test_mm_mask3_fnmadd_pd() {
2611        let a = _mm_set1_pd(1.);
2612        let b = _mm_set_pd(0., 1.);
2613        let c = _mm_set1_pd(1.);
2614        let r = _mm_mask3_fnmadd_pd(a, b, c, 0);
2615        assert_eq_m128d(r, c);
2616        let r = _mm_mask3_fnmadd_pd(a, b, c, 0b00000011);
2617        let e = _mm_set_pd(1., 0.);
2618        assert_eq_m128d(r, e);
2619    }
2620
2621    #[simd_test(enable = "avx512f")]
2622    unsafe fn test_mm512_fnmsub_pd() {
2623        let a = _mm512_set1_pd(1.);
2624        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2625        let c = _mm512_set1_pd(1.);
2626        let r = _mm512_fnmsub_pd(a, b, c);
2627        let e = _mm512_setr_pd(-1., -2., -3., -4., -5., -6., -7., -8.);
2628        assert_eq_m512d(r, e);
2629    }
2630
2631    #[simd_test(enable = "avx512f")]
2632    unsafe fn test_mm512_mask_fnmsub_pd() {
2633        let a = _mm512_set1_pd(1.);
2634        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2635        let c = _mm512_set1_pd(1.);
2636        let r = _mm512_mask_fnmsub_pd(a, 0, b, c);
2637        assert_eq_m512d(r, a);
2638        let r = _mm512_mask_fnmsub_pd(a, 0b00001111, b, c);
2639        let e = _mm512_setr_pd(-1., -2., -3., -4., 1., 1., 1., 1.);
2640        assert_eq_m512d(r, e);
2641    }
2642
2643    #[simd_test(enable = "avx512f")]
2644    unsafe fn test_mm512_maskz_fnmsub_pd() {
2645        let a = _mm512_set1_pd(1.);
2646        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2647        let c = _mm512_set1_pd(1.);
2648        let r = _mm512_maskz_fnmsub_pd(0, a, b, c);
2649        assert_eq_m512d(r, _mm512_setzero_pd());
2650        let r = _mm512_maskz_fnmsub_pd(0b00001111, a, b, c);
2651        let e = _mm512_setr_pd(-1., -2., -3., -4., 0., 0., 0., 0.);
2652        assert_eq_m512d(r, e);
2653    }
2654
2655    #[simd_test(enable = "avx512f")]
2656    unsafe fn test_mm512_mask3_fnmsub_pd() {
2657        let a = _mm512_set1_pd(1.);
2658        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2659        let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2660        let r = _mm512_mask3_fnmsub_pd(a, b, c, 0);
2661        assert_eq_m512d(r, c);
2662        let r = _mm512_mask3_fnmsub_pd(a, b, c, 0b00001111);
2663        let e = _mm512_setr_pd(-1., -2., -3., -4., 2., 2., 2., 2.);
2664        assert_eq_m512d(r, e);
2665    }
2666
2667    #[simd_test(enable = "avx512f,avx512vl")]
2668    unsafe fn test_mm256_mask_fnmsub_pd() {
2669        let a = _mm256_set1_pd(1.);
2670        let b = _mm256_set_pd(0., 1., 2., 3.);
2671        let c = _mm256_set1_pd(1.);
2672        let r = _mm256_mask_fnmsub_pd(a, 0, b, c);
2673        assert_eq_m256d(r, a);
2674        let r = _mm256_mask_fnmsub_pd(a, 0b00001111, b, c);
2675        let e = _mm256_set_pd(-1., -2., -3., -4.);
2676        assert_eq_m256d(r, e);
2677    }
2678
2679    #[simd_test(enable = "avx512f,avx512vl")]
2680    unsafe fn test_mm256_maskz_fnmsub_pd() {
2681        let a = _mm256_set1_pd(1.);
2682        let b = _mm256_set_pd(0., 1., 2., 3.);
2683        let c = _mm256_set1_pd(1.);
2684        let r = _mm256_maskz_fnmsub_pd(0, a, b, c);
2685        assert_eq_m256d(r, _mm256_setzero_pd());
2686        let r = _mm256_maskz_fnmsub_pd(0b00001111, a, b, c);
2687        let e = _mm256_set_pd(-1., -2., -3., -4.);
2688        assert_eq_m256d(r, e);
2689    }
2690
2691    #[simd_test(enable = "avx512f,avx512vl")]
2692    unsafe fn test_mm256_mask3_fnmsub_pd() {
2693        let a = _mm256_set1_pd(1.);
2694        let b = _mm256_set_pd(0., 1., 2., 3.);
2695        let c = _mm256_set1_pd(1.);
2696        let r = _mm256_mask3_fnmsub_pd(a, b, c, 0);
2697        assert_eq_m256d(r, c);
2698        let r = _mm256_mask3_fnmsub_pd(a, b, c, 0b00001111);
2699        let e = _mm256_set_pd(-1., -2., -3., -4.);
2700        assert_eq_m256d(r, e);
2701    }
2702
2703    #[simd_test(enable = "avx512f,avx512vl")]
2704    unsafe fn test_mm_mask_fnmsub_pd() {
2705        let a = _mm_set1_pd(1.);
2706        let b = _mm_set_pd(0., 1.);
2707        let c = _mm_set1_pd(1.);
2708        let r = _mm_mask_fnmsub_pd(a, 0, b, c);
2709        assert_eq_m128d(r, a);
2710        let r = _mm_mask_fnmsub_pd(a, 0b00000011, b, c);
2711        let e = _mm_set_pd(-1., -2.);
2712        assert_eq_m128d(r, e);
2713    }
2714
2715    #[simd_test(enable = "avx512f,avx512vl")]
2716    unsafe fn test_mm_maskz_fnmsub_pd() {
2717        let a = _mm_set1_pd(1.);
2718        let b = _mm_set_pd(0., 1.);
2719        let c = _mm_set1_pd(1.);
2720        let r = _mm_maskz_fnmsub_pd(0, a, b, c);
2721        assert_eq_m128d(r, _mm_setzero_pd());
2722        let r = _mm_maskz_fnmsub_pd(0b00000011, a, b, c);
2723        let e = _mm_set_pd(-1., -2.);
2724        assert_eq_m128d(r, e);
2725    }
2726
2727    #[simd_test(enable = "avx512f,avx512vl")]
2728    unsafe fn test_mm_mask3_fnmsub_pd() {
2729        let a = _mm_set1_pd(1.);
2730        let b = _mm_set_pd(0., 1.);
2731        let c = _mm_set1_pd(1.);
2732        let r = _mm_mask3_fnmsub_pd(a, b, c, 0);
2733        assert_eq_m128d(r, c);
2734        let r = _mm_mask3_fnmsub_pd(a, b, c, 0b00000011);
2735        let e = _mm_set_pd(-1., -2.);
2736        assert_eq_m128d(r, e);
2737    }
2738
2739    #[simd_test(enable = "avx512f")]
2740    unsafe fn test_mm512_rcp14_pd() {
2741        let a = _mm512_set1_pd(3.);
2742        let r = _mm512_rcp14_pd(a);
2743        let e = _mm512_set1_pd(0.3333320617675781);
2744        assert_eq_m512d(r, e);
2745    }
2746
2747    #[simd_test(enable = "avx512f")]
2748    unsafe fn test_mm512_mask_rcp14_pd() {
2749        let a = _mm512_set1_pd(3.);
2750        let r = _mm512_mask_rcp14_pd(a, 0, a);
2751        assert_eq_m512d(r, a);
2752        let r = _mm512_mask_rcp14_pd(a, 0b11110000, a);
2753        #[rustfmt::skip]
2754        let e = _mm512_setr_pd(
2755            3., 3., 3., 3.,
2756            0.3333320617675781, 0.3333320617675781, 0.3333320617675781, 0.3333320617675781,
2757        );
2758        assert_eq_m512d(r, e);
2759    }
2760
2761    #[simd_test(enable = "avx512f")]
2762    unsafe fn test_mm512_maskz_rcp14_pd() {
2763        let a = _mm512_set1_pd(3.);
2764        let r = _mm512_maskz_rcp14_pd(0, a);
2765        assert_eq_m512d(r, _mm512_setzero_pd());
2766        let r = _mm512_maskz_rcp14_pd(0b11110000, a);
2767        #[rustfmt::skip]
2768        let e = _mm512_setr_pd(
2769            0., 0., 0., 0.,
2770            0.3333320617675781, 0.3333320617675781, 0.3333320617675781, 0.3333320617675781,
2771        );
2772        assert_eq_m512d(r, e);
2773    }
2774
2775    #[simd_test(enable = "avx512f,avx512vl")]
2776    unsafe fn test_mm256_rcp14_pd() {
2777        let a = _mm256_set1_pd(3.);
2778        let r = _mm256_rcp14_pd(a);
2779        let e = _mm256_set1_pd(0.3333320617675781);
2780        assert_eq_m256d(r, e);
2781    }
2782
2783    #[simd_test(enable = "avx512f,avx512vl")]
2784    unsafe fn test_mm256_mask_rcp14_pd() {
2785        let a = _mm256_set1_pd(3.);
2786        let r = _mm256_mask_rcp14_pd(a, 0, a);
2787        assert_eq_m256d(r, a);
2788        let r = _mm256_mask_rcp14_pd(a, 0b00001111, a);
2789        let e = _mm256_set1_pd(0.3333320617675781);
2790        assert_eq_m256d(r, e);
2791    }
2792
2793    #[simd_test(enable = "avx512f,avx512vl")]
2794    unsafe fn test_mm256_maskz_rcp14_pd() {
2795        let a = _mm256_set1_pd(3.);
2796        let r = _mm256_maskz_rcp14_pd(0, a);
2797        assert_eq_m256d(r, _mm256_setzero_pd());
2798        let r = _mm256_maskz_rcp14_pd(0b00001111, a);
2799        let e = _mm256_set1_pd(0.3333320617675781);
2800        assert_eq_m256d(r, e);
2801    }
2802
2803    #[simd_test(enable = "avx512f,avx512vl")]
2804    unsafe fn test_mm_rcp14_pd() {
2805        let a = _mm_set1_pd(3.);
2806        let r = _mm_rcp14_pd(a);
2807        let e = _mm_set1_pd(0.3333320617675781);
2808        assert_eq_m128d(r, e);
2809    }
2810
2811    #[simd_test(enable = "avx512f,avx512vl")]
2812    unsafe fn test_mm_mask_rcp14_pd() {
2813        let a = _mm_set1_pd(3.);
2814        let r = _mm_mask_rcp14_pd(a, 0, a);
2815        assert_eq_m128d(r, a);
2816        let r = _mm_mask_rcp14_pd(a, 0b00000011, a);
2817        let e = _mm_set1_pd(0.3333320617675781);
2818        assert_eq_m128d(r, e);
2819    }
2820
2821    #[simd_test(enable = "avx512f,avx512vl")]
2822    unsafe fn test_mm_maskz_rcp14_pd() {
2823        let a = _mm_set1_pd(3.);
2824        let r = _mm_maskz_rcp14_pd(0, a);
2825        assert_eq_m128d(r, _mm_setzero_pd());
2826        let r = _mm_maskz_rcp14_pd(0b00000011, a);
2827        let e = _mm_set1_pd(0.3333320617675781);
2828        assert_eq_m128d(r, e);
2829    }
2830
2831    #[simd_test(enable = "avx512f")]
2832    unsafe fn test_mm512_rsqrt14_pd() {
2833        let a = _mm512_set1_pd(3.);
2834        let r = _mm512_rsqrt14_pd(a);
2835        let e = _mm512_set1_pd(0.5773391723632813);
2836        assert_eq_m512d(r, e);
2837    }
2838
2839    #[simd_test(enable = "avx512f")]
2840    unsafe fn test_mm512_mask_rsqrt14_pd() {
2841        let a = _mm512_set1_pd(3.);
2842        let r = _mm512_mask_rsqrt14_pd(a, 0, a);
2843        assert_eq_m512d(r, a);
2844        let r = _mm512_mask_rsqrt14_pd(a, 0b11110000, a);
2845        #[rustfmt::skip]
2846        let e = _mm512_setr_pd(
2847            3., 3., 3., 3.,
2848            0.5773391723632813, 0.5773391723632813, 0.5773391723632813, 0.5773391723632813,
2849        );
2850        assert_eq_m512d(r, e);
2851    }
2852
2853    #[simd_test(enable = "avx512f")]
2854    unsafe fn test_mm512_maskz_rsqrt14_pd() {
2855        let a = _mm512_set1_pd(3.);
2856        let r = _mm512_maskz_rsqrt14_pd(0, a);
2857        assert_eq_m512d(r, _mm512_setzero_pd());
2858        let r = _mm512_maskz_rsqrt14_pd(0b11110000, a);
2859        #[rustfmt::skip]
2860        let e = _mm512_setr_pd(
2861            0., 0., 0., 0.,
2862            0.5773391723632813, 0.5773391723632813, 0.5773391723632813, 0.5773391723632813,
2863        );
2864        assert_eq_m512d(r, e);
2865    }
2866
2867    #[simd_test(enable = "avx512f,avx512vl")]
2868    unsafe fn test_mm256_rsqrt14_pd() {
2869        let a = _mm256_set1_pd(3.);
2870        let r = _mm256_rsqrt14_pd(a);
2871        let e = _mm256_set1_pd(0.5773391723632813);
2872        assert_eq_m256d(r, e);
2873    }
2874
2875    #[simd_test(enable = "avx512f,avx512vl")]
2876    unsafe fn test_mm256_mask_rsqrt14_pd() {
2877        let a = _mm256_set1_pd(3.);
2878        let r = _mm256_mask_rsqrt14_pd(a, 0, a);
2879        assert_eq_m256d(r, a);
2880        let r = _mm256_mask_rsqrt14_pd(a, 0b00001111, a);
2881        let e = _mm256_set1_pd(0.5773391723632813);
2882        assert_eq_m256d(r, e);
2883    }
2884
2885    #[simd_test(enable = "avx512f,avx512vl")]
2886    unsafe fn test_mm256_maskz_rsqrt14_pd() {
2887        let a = _mm256_set1_pd(3.);
2888        let r = _mm256_maskz_rsqrt14_pd(0, a);
2889        assert_eq_m256d(r, _mm256_setzero_pd());
2890        let r = _mm256_maskz_rsqrt14_pd(0b00001111, a);
2891        let e = _mm256_set1_pd(0.5773391723632813);
2892        assert_eq_m256d(r, e);
2893    }
2894
2895    #[simd_test(enable = "avx512f,avx512vl")]
2896    unsafe fn test_mm_rsqrt14_pd() {
2897        let a = _mm_set1_pd(3.);
2898        let r = _mm_rsqrt14_pd(a);
2899        let e = _mm_set1_pd(0.5773391723632813);
2900        assert_eq_m128d(r, e);
2901    }
2902
2903    #[simd_test(enable = "avx512f,avx512vl")]
2904    unsafe fn test_mm_mask_rsqrt14_pd() {
2905        let a = _mm_set1_pd(3.);
2906        let r = _mm_mask_rsqrt14_pd(a, 0, a);
2907        assert_eq_m128d(r, a);
2908        let r = _mm_mask_rsqrt14_pd(a, 0b00000011, a);
2909        let e = _mm_set1_pd(0.5773391723632813);
2910        assert_eq_m128d(r, e);
2911    }
2912
2913    #[simd_test(enable = "avx512f,avx512vl")]
2914    unsafe fn test_mm_maskz_rsqrt14_pd() {
2915        let a = _mm_set1_pd(3.);
2916        let r = _mm_maskz_rsqrt14_pd(0, a);
2917        assert_eq_m128d(r, _mm_setzero_pd());
2918        let r = _mm_maskz_rsqrt14_pd(0b00000011, a);
2919        let e = _mm_set1_pd(0.5773391723632813);
2920        assert_eq_m128d(r, e);
2921    }
2922
2923    #[simd_test(enable = "avx512f")]
2924    unsafe fn test_mm512_getexp_pd() {
2925        let a = _mm512_set1_pd(3.);
2926        let r = _mm512_getexp_pd(a);
2927        let e = _mm512_set1_pd(1.);
2928        assert_eq_m512d(r, e);
2929    }
2930
2931    #[simd_test(enable = "avx512f")]
2932    unsafe fn test_mm512_mask_getexp_pd() {
2933        let a = _mm512_set1_pd(3.);
2934        let r = _mm512_mask_getexp_pd(a, 0, a);
2935        assert_eq_m512d(r, a);
2936        let r = _mm512_mask_getexp_pd(a, 0b11110000, a);
2937        let e = _mm512_setr_pd(3., 3., 3., 3., 1., 1., 1., 1.);
2938        assert_eq_m512d(r, e);
2939    }
2940
2941    #[simd_test(enable = "avx512f")]
2942    unsafe fn test_mm512_maskz_getexp_pd() {
2943        let a = _mm512_set1_pd(3.);
2944        let r = _mm512_maskz_getexp_pd(0, a);
2945        assert_eq_m512d(r, _mm512_setzero_pd());
2946        let r = _mm512_maskz_getexp_pd(0b11110000, a);
2947        let e = _mm512_setr_pd(0., 0., 0., 0., 1., 1., 1., 1.);
2948        assert_eq_m512d(r, e);
2949    }
2950
2951    #[simd_test(enable = "avx512f,avx512vl")]
2952    unsafe fn test_mm256_getexp_pd() {
2953        let a = _mm256_set1_pd(3.);
2954        let r = _mm256_getexp_pd(a);
2955        let e = _mm256_set1_pd(1.);
2956        assert_eq_m256d(r, e);
2957    }
2958
2959    #[simd_test(enable = "avx512f,avx512vl")]
2960    unsafe fn test_mm256_mask_getexp_pd() {
2961        let a = _mm256_set1_pd(3.);
2962        let r = _mm256_mask_getexp_pd(a, 0, a);
2963        assert_eq_m256d(r, a);
2964        let r = _mm256_mask_getexp_pd(a, 0b00001111, a);
2965        let e = _mm256_set1_pd(1.);
2966        assert_eq_m256d(r, e);
2967    }
2968
2969    #[simd_test(enable = "avx512f,avx512vl")]
2970    unsafe fn test_mm256_maskz_getexp_pd() {
2971        let a = _mm256_set1_pd(3.);
2972        let r = _mm256_maskz_getexp_pd(0, a);
2973        assert_eq_m256d(r, _mm256_setzero_pd());
2974        let r = _mm256_maskz_getexp_pd(0b00001111, a);
2975        let e = _mm256_set1_pd(1.);
2976        assert_eq_m256d(r, e);
2977    }
2978
2979    #[simd_test(enable = "avx512f,avx512vl")]
2980    unsafe fn test_mm_getexp_pd() {
2981        let a = _mm_set1_pd(3.);
2982        let r = _mm_getexp_pd(a);
2983        let e = _mm_set1_pd(1.);
2984        assert_eq_m128d(r, e);
2985    }
2986
2987    #[simd_test(enable = "avx512f,avx512vl")]
2988    unsafe fn test_mm_mask_getexp_pd() {
2989        let a = _mm_set1_pd(3.);
2990        let r = _mm_mask_getexp_pd(a, 0, a);
2991        assert_eq_m128d(r, a);
2992        let r = _mm_mask_getexp_pd(a, 0b00000011, a);
2993        let e = _mm_set1_pd(1.);
2994        assert_eq_m128d(r, e);
2995    }
2996
2997    #[simd_test(enable = "avx512f,avx512vl")]
2998    unsafe fn test_mm_maskz_getexp_pd() {
2999        let a = _mm_set1_pd(3.);
3000        let r = _mm_maskz_getexp_pd(0, a);
3001        assert_eq_m128d(r, _mm_setzero_pd());
3002        let r = _mm_maskz_getexp_pd(0b00000011, a);
3003        let e = _mm_set1_pd(1.);
3004        assert_eq_m128d(r, e);
3005    }
3006
3007    #[simd_test(enable = "avx512f")]
3008    unsafe fn test_mm512_roundscale_pd() {
3009        let a = _mm512_set1_pd(1.1);
3010        let r = _mm512_roundscale_pd::<0b00_00_00_00>(a);
3011        let e = _mm512_set1_pd(1.0);
3012        assert_eq_m512d(r, e);
3013    }
3014
3015    #[simd_test(enable = "avx512f")]
3016    unsafe fn test_mm512_mask_roundscale_pd() {
3017        let a = _mm512_set1_pd(1.1);
3018        let r = _mm512_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
3019        let e = _mm512_set1_pd(1.1);
3020        assert_eq_m512d(r, e);
3021        let r = _mm512_mask_roundscale_pd::<0b00_00_00_00>(a, 0b11111111, a);
3022        let e = _mm512_set1_pd(1.0);
3023        assert_eq_m512d(r, e);
3024    }
3025
3026    #[simd_test(enable = "avx512f")]
3027    unsafe fn test_mm512_maskz_roundscale_pd() {
3028        let a = _mm512_set1_pd(1.1);
3029        let r = _mm512_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
3030        assert_eq_m512d(r, _mm512_setzero_pd());
3031        let r = _mm512_maskz_roundscale_pd::<0b00_00_00_00>(0b11111111, a);
3032        let e = _mm512_set1_pd(1.0);
3033        assert_eq_m512d(r, e);
3034    }
3035
3036    #[simd_test(enable = "avx512f,avx512vl")]
3037    unsafe fn test_mm256_roundscale_pd() {
3038        let a = _mm256_set1_pd(1.1);
3039        let r = _mm256_roundscale_pd::<0b00_00_00_00>(a);
3040        let e = _mm256_set1_pd(1.0);
3041        assert_eq_m256d(r, e);
3042    }
3043
3044    #[simd_test(enable = "avx512f,avx512vl")]
3045    unsafe fn test_mm256_mask_roundscale_pd() {
3046        let a = _mm256_set1_pd(1.1);
3047        let r = _mm256_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
3048        assert_eq_m256d(r, a);
3049        let r = _mm256_mask_roundscale_pd::<0b00_00_00_00>(a, 0b00001111, a);
3050        let e = _mm256_set1_pd(1.0);
3051        assert_eq_m256d(r, e);
3052    }
3053
3054    #[simd_test(enable = "avx512f,avx512vl")]
3055    unsafe fn test_mm256_maskz_roundscale_pd() {
3056        let a = _mm256_set1_pd(1.1);
3057        let r = _mm256_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
3058        assert_eq_m256d(r, _mm256_setzero_pd());
3059        let r = _mm256_maskz_roundscale_pd::<0b00_00_00_00>(0b00001111, a);
3060        let e = _mm256_set1_pd(1.0);
3061        assert_eq_m256d(r, e);
3062    }
3063
3064    #[simd_test(enable = "avx512f,avx512vl")]
3065    unsafe fn test_mm_roundscale_pd() {
3066        let a = _mm_set1_pd(1.1);
3067        let r = _mm_roundscale_pd::<0b00_00_00_00>(a);
3068        let e = _mm_set1_pd(1.0);
3069        assert_eq_m128d(r, e);
3070    }
3071
3072    #[simd_test(enable = "avx512f,avx512vl")]
3073    unsafe fn test_mm_mask_roundscale_pd() {
3074        let a = _mm_set1_pd(1.1);
3075        let r = _mm_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
3076        let e = _mm_set1_pd(1.1);
3077        assert_eq_m128d(r, e);
3078        let r = _mm_mask_roundscale_pd::<0b00_00_00_00>(a, 0b00000011, a);
3079        let e = _mm_set1_pd(1.0);
3080        assert_eq_m128d(r, e);
3081    }
3082
3083    #[simd_test(enable = "avx512f,avx512vl")]
3084    unsafe fn test_mm_maskz_roundscale_pd() {
3085        let a = _mm_set1_pd(1.1);
3086        let r = _mm_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
3087        assert_eq_m128d(r, _mm_setzero_pd());
3088        let r = _mm_maskz_roundscale_pd::<0b00_00_00_00>(0b00000011, a);
3089        let e = _mm_set1_pd(1.0);
3090        assert_eq_m128d(r, e);
3091    }
3092
3093    #[simd_test(enable = "avx512f")]
3094    unsafe fn test_mm512_scalef_pd() {
3095        let a = _mm512_set1_pd(1.);
3096        let b = _mm512_set1_pd(3.);
3097        let r = _mm512_scalef_pd(a, b);
3098        let e = _mm512_set1_pd(8.);
3099        assert_eq_m512d(r, e);
3100    }
3101
3102    #[simd_test(enable = "avx512f")]
3103    unsafe fn test_mm512_mask_scalef_pd() {
3104        let a = _mm512_set1_pd(1.);
3105        let b = _mm512_set1_pd(3.);
3106        let r = _mm512_mask_scalef_pd(a, 0, a, b);
3107        assert_eq_m512d(r, a);
3108        let r = _mm512_mask_scalef_pd(a, 0b11110000, a, b);
3109        let e = _mm512_set_pd(8., 8., 8., 8., 1., 1., 1., 1.);
3110        assert_eq_m512d(r, e);
3111    }
3112
3113    #[simd_test(enable = "avx512f")]
3114    unsafe fn test_mm512_maskz_scalef_pd() {
3115        let a = _mm512_set1_pd(1.);
3116        let b = _mm512_set1_pd(3.);
3117        let r = _mm512_maskz_scalef_pd(0, a, b);
3118        assert_eq_m512d(r, _mm512_setzero_pd());
3119        let r = _mm512_maskz_scalef_pd(0b11110000, a, b);
3120        let e = _mm512_set_pd(8., 8., 8., 8., 0., 0., 0., 0.);
3121        assert_eq_m512d(r, e);
3122    }
3123
3124    #[simd_test(enable = "avx512f,avx512vl")]
3125    unsafe fn test_mm256_scalef_pd() {
3126        let a = _mm256_set1_pd(1.);
3127        let b = _mm256_set1_pd(3.);
3128        let r = _mm256_scalef_pd(a, b);
3129        let e = _mm256_set1_pd(8.);
3130        assert_eq_m256d(r, e);
3131    }
3132
3133    #[simd_test(enable = "avx512f,avx512vl")]
3134    unsafe fn test_mm256_mask_scalef_pd() {
3135        let a = _mm256_set1_pd(1.);
3136        let b = _mm256_set1_pd(3.);
3137        let r = _mm256_mask_scalef_pd(a, 0, a, b);
3138        assert_eq_m256d(r, a);
3139        let r = _mm256_mask_scalef_pd(a, 0b00001111, a, b);
3140        let e = _mm256_set1_pd(8.);
3141        assert_eq_m256d(r, e);
3142    }
3143
3144    #[simd_test(enable = "avx512f,avx512vl")]
3145    unsafe fn test_mm256_maskz_scalef_pd() {
3146        let a = _mm256_set1_pd(1.);
3147        let b = _mm256_set1_pd(3.);
3148        let r = _mm256_maskz_scalef_pd(0, a, b);
3149        assert_eq_m256d(r, _mm256_setzero_pd());
3150        let r = _mm256_maskz_scalef_pd(0b00001111, a, b);
3151        let e = _mm256_set1_pd(8.);
3152        assert_eq_m256d(r, e);
3153    }
3154
3155    #[simd_test(enable = "avx512f,avx512vl")]
3156    unsafe fn test_mm_scalef_pd() {
3157        let a = _mm_set1_pd(1.);
3158        let b = _mm_set1_pd(3.);
3159        let r = _mm_scalef_pd(a, b);
3160        let e = _mm_set1_pd(8.);
3161        assert_eq_m128d(r, e);
3162    }
3163
3164    #[simd_test(enable = "avx512f,avx512vl")]
3165    unsafe fn test_mm_mask_scalef_pd() {
3166        let a = _mm_set1_pd(1.);
3167        let b = _mm_set1_pd(3.);
3168        let r = _mm_mask_scalef_pd(a, 0, a, b);
3169        assert_eq_m128d(r, a);
3170        let r = _mm_mask_scalef_pd(a, 0b00000011, a, b);
3171        let e = _mm_set1_pd(8.);
3172        assert_eq_m128d(r, e);
3173    }
3174
3175    #[simd_test(enable = "avx512f,avx512vl")]
3176    unsafe fn test_mm_maskz_scalef_pd() {
3177        let a = _mm_set1_pd(1.);
3178        let b = _mm_set1_pd(3.);
3179        let r = _mm_maskz_scalef_pd(0, a, b);
3180        assert_eq_m128d(r, _mm_setzero_pd());
3181        let r = _mm_maskz_scalef_pd(0b00000011, a, b);
3182        let e = _mm_set1_pd(8.);
3183        assert_eq_m128d(r, e);
3184    }
3185
3186    #[simd_test(enable = "avx512f")]
3187    unsafe fn test_mm512_fixupimm_pd() {
3188        let a = _mm512_set1_pd(f64::NAN);
3189        let b = _mm512_set1_pd(f64::MAX);
3190        let c = _mm512_set1_epi64(i32::MAX as i64);
3191        let r = _mm512_fixupimm_pd::<5>(a, b, c);
3192        let e = _mm512_set1_pd(0.0);
3193        assert_eq_m512d(r, e);
3194    }
3195
3196    #[simd_test(enable = "avx512f")]
3197    unsafe fn test_mm512_mask_fixupimm_pd() {
3198        let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
3199        let b = _mm512_set1_pd(f64::MAX);
3200        let c = _mm512_set1_epi64(i32::MAX as i64);
3201        let r = _mm512_mask_fixupimm_pd::<5>(a, 0b11110000, b, c);
3202        let e = _mm512_set_pd(0., 0., 0., 0., 1., 1., 1., 1.);
3203        assert_eq_m512d(r, e);
3204    }
3205
3206    #[simd_test(enable = "avx512f")]
3207    unsafe fn test_mm512_maskz_fixupimm_pd() {
3208        let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
3209        let b = _mm512_set1_pd(f64::MAX);
3210        let c = _mm512_set1_epi64(i32::MAX as i64);
3211        let r = _mm512_maskz_fixupimm_pd::<5>(0b11110000, a, b, c);
3212        let e = _mm512_set_pd(0., 0., 0., 0., 0., 0., 0., 0.);
3213        assert_eq_m512d(r, e);
3214    }
3215
3216    #[simd_test(enable = "avx512f,avx512vl")]
3217    unsafe fn test_mm256_fixupimm_pd() {
3218        let a = _mm256_set1_pd(f64::NAN);
3219        let b = _mm256_set1_pd(f64::MAX);
3220        let c = _mm256_set1_epi64x(i32::MAX as i64);
3221        let r = _mm256_fixupimm_pd::<5>(a, b, c);
3222        let e = _mm256_set1_pd(0.0);
3223        assert_eq_m256d(r, e);
3224    }
3225
3226    #[simd_test(enable = "avx512f,avx512vl")]
3227    unsafe fn test_mm256_mask_fixupimm_pd() {
3228        let a = _mm256_set1_pd(f64::NAN);
3229        let b = _mm256_set1_pd(f64::MAX);
3230        let c = _mm256_set1_epi64x(i32::MAX as i64);
3231        let r = _mm256_mask_fixupimm_pd::<5>(a, 0b00001111, b, c);
3232        let e = _mm256_set1_pd(0.0);
3233        assert_eq_m256d(r, e);
3234    }
3235
3236    #[simd_test(enable = "avx512f,avx512vl")]
3237    unsafe fn test_mm256_maskz_fixupimm_pd() {
3238        let a = _mm256_set1_pd(f64::NAN);
3239        let b = _mm256_set1_pd(f64::MAX);
3240        let c = _mm256_set1_epi64x(i32::MAX as i64);
3241        let r = _mm256_maskz_fixupimm_pd::<5>(0b00001111, a, b, c);
3242        let e = _mm256_set1_pd(0.0);
3243        assert_eq_m256d(r, e);
3244    }
3245
3246    #[simd_test(enable = "avx512f,avx512vl")]
3247    unsafe fn test_mm_fixupimm_pd() {
3248        let a = _mm_set1_pd(f64::NAN);
3249        let b = _mm_set1_pd(f64::MAX);
3250        let c = _mm_set1_epi64x(i32::MAX as i64);
3251        let r = _mm_fixupimm_pd::<5>(a, b, c);
3252        let e = _mm_set1_pd(0.0);
3253        assert_eq_m128d(r, e);
3254    }
3255
3256    #[simd_test(enable = "avx512f,avx512vl")]
3257    unsafe fn test_mm_mask_fixupimm_pd() {
3258        let a = _mm_set1_pd(f64::NAN);
3259        let b = _mm_set1_pd(f64::MAX);
3260        let c = _mm_set1_epi64x(i32::MAX as i64);
3261        let r = _mm_mask_fixupimm_pd::<5>(a, 0b00000011, b, c);
3262        let e = _mm_set1_pd(0.0);
3263        assert_eq_m128d(r, e);
3264    }
3265
3266    #[simd_test(enable = "avx512f,avx512vl")]
3267    unsafe fn test_mm_maskz_fixupimm_pd() {
3268        let a = _mm_set1_pd(f64::NAN);
3269        let b = _mm_set1_pd(f64::MAX);
3270        let c = _mm_set1_epi64x(i32::MAX as i64);
3271        let r = _mm_maskz_fixupimm_pd::<5>(0b00000011, a, b, c);
3272        let e = _mm_set1_pd(0.0);
3273        assert_eq_m128d(r, e);
3274    }
3275
3276    #[simd_test(enable = "avx512f")]
3277    unsafe fn test_mm512_ternarylogic_epi64() {
3278        let a = _mm512_set1_epi64(1 << 2);
3279        let b = _mm512_set1_epi64(1 << 1);
3280        let c = _mm512_set1_epi64(1 << 0);
3281        let r = _mm512_ternarylogic_epi64::<8>(a, b, c);
3282        let e = _mm512_set1_epi64(0);
3283        assert_eq_m512i(r, e);
3284    }
3285
3286    #[simd_test(enable = "avx512f")]
3287    unsafe fn test_mm512_mask_ternarylogic_epi64() {
3288        let src = _mm512_set1_epi64(1 << 2);
3289        let a = _mm512_set1_epi64(1 << 1);
3290        let b = _mm512_set1_epi64(1 << 0);
3291        let r = _mm512_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3292        assert_eq_m512i(r, src);
3293        let r = _mm512_mask_ternarylogic_epi64::<8>(src, 0b11111111, a, b);
3294        let e = _mm512_set1_epi64(0);
3295        assert_eq_m512i(r, e);
3296    }
3297
3298    #[simd_test(enable = "avx512f")]
3299    unsafe fn test_mm512_maskz_ternarylogic_epi64() {
3300        let a = _mm512_set1_epi64(1 << 2);
3301        let b = _mm512_set1_epi64(1 << 1);
3302        let c = _mm512_set1_epi64(1 << 0);
3303        let r = _mm512_maskz_ternarylogic_epi64::<8>(0, a, b, c);
3304        assert_eq_m512i(r, _mm512_setzero_si512());
3305        let r = _mm512_maskz_ternarylogic_epi64::<8>(0b11111111, a, b, c);
3306        let e = _mm512_set1_epi64(0);
3307        assert_eq_m512i(r, e);
3308    }
3309
3310    #[simd_test(enable = "avx512f,avx512vl")]
3311    unsafe fn test_mm256_ternarylogic_epi64() {
3312        let a = _mm256_set1_epi64x(1 << 2);
3313        let b = _mm256_set1_epi64x(1 << 1);
3314        let c = _mm256_set1_epi64x(1 << 0);
3315        let r = _mm256_ternarylogic_epi64::<8>(a, b, c);
3316        let e = _mm256_set1_epi64x(0);
3317        assert_eq_m256i(r, e);
3318    }
3319
3320    #[simd_test(enable = "avx512f,avx512vl")]
3321    unsafe fn test_mm256_mask_ternarylogic_epi64() {
3322        let src = _mm256_set1_epi64x(1 << 2);
3323        let a = _mm256_set1_epi64x(1 << 1);
3324        let b = _mm256_set1_epi64x(1 << 0);
3325        let r = _mm256_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3326        assert_eq_m256i(r, src);
3327        let r = _mm256_mask_ternarylogic_epi64::<8>(src, 0b00001111, a, b);
3328        let e = _mm256_set1_epi64x(0);
3329        assert_eq_m256i(r, e);
3330    }
3331
3332    #[simd_test(enable = "avx512f,avx512vl")]
3333    unsafe fn test_mm256_maskz_ternarylogic_epi64() {
3334        let a = _mm256_set1_epi64x(1 << 2);
3335        let b = _mm256_set1_epi64x(1 << 1);
3336        let c = _mm256_set1_epi64x(1 << 0);
3337        let r = _mm256_maskz_ternarylogic_epi64::<9>(0, a, b, c);
3338        assert_eq_m256i(r, _mm256_setzero_si256());
3339        let r = _mm256_maskz_ternarylogic_epi64::<8>(0b00001111, a, b, c);
3340        let e = _mm256_set1_epi64x(0);
3341        assert_eq_m256i(r, e);
3342    }
3343
3344    #[simd_test(enable = "avx512f,avx512vl")]
3345    unsafe fn test_mm_ternarylogic_epi64() {
3346        let a = _mm_set1_epi64x(1 << 2);
3347        let b = _mm_set1_epi64x(1 << 1);
3348        let c = _mm_set1_epi64x(1 << 0);
3349        let r = _mm_ternarylogic_epi64::<8>(a, b, c);
3350        let e = _mm_set1_epi64x(0);
3351        assert_eq_m128i(r, e);
3352    }
3353
3354    #[simd_test(enable = "avx512f,avx512vl")]
3355    unsafe fn test_mm_mask_ternarylogic_epi64() {
3356        let src = _mm_set1_epi64x(1 << 2);
3357        let a = _mm_set1_epi64x(1 << 1);
3358        let b = _mm_set1_epi64x(1 << 0);
3359        let r = _mm_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3360        assert_eq_m128i(r, src);
3361        let r = _mm_mask_ternarylogic_epi64::<8>(src, 0b00000011, a, b);
3362        let e = _mm_set1_epi64x(0);
3363        assert_eq_m128i(r, e);
3364    }
3365
3366    #[simd_test(enable = "avx512f,avx512vl")]
3367    unsafe fn test_mm_maskz_ternarylogic_epi64() {
3368        let a = _mm_set1_epi64x(1 << 2);
3369        let b = _mm_set1_epi64x(1 << 1);
3370        let c = _mm_set1_epi64x(1 << 0);
3371        let r = _mm_maskz_ternarylogic_epi64::<9>(0, a, b, c);
3372        assert_eq_m128i(r, _mm_setzero_si128());
3373        let r = _mm_maskz_ternarylogic_epi64::<8>(0b00000011, a, b, c);
3374        let e = _mm_set1_epi64x(0);
3375        assert_eq_m128i(r, e);
3376    }
3377
3378    #[simd_test(enable = "avx512f")]
3379    unsafe fn test_mm512_getmant_pd() {
3380        let a = _mm512_set1_pd(10.);
3381        let r = _mm512_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3382        let e = _mm512_set1_pd(1.25);
3383        assert_eq_m512d(r, e);
3384    }
3385
3386    #[simd_test(enable = "avx512f")]
3387    unsafe fn test_mm512_mask_getmant_pd() {
3388        let a = _mm512_set1_pd(10.);
3389        let r = _mm512_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3390        assert_eq_m512d(r, a);
3391        let r = _mm512_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b11110000, a);
3392        let e = _mm512_setr_pd(10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25);
3393        assert_eq_m512d(r, e);
3394    }
3395
3396    #[simd_test(enable = "avx512f")]
3397    unsafe fn test_mm512_maskz_getmant_pd() {
3398        let a = _mm512_set1_pd(10.);
3399        let r = _mm512_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3400        assert_eq_m512d(r, _mm512_setzero_pd());
3401        let r = _mm512_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b11110000, a);
3402        let e = _mm512_setr_pd(0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25);
3403        assert_eq_m512d(r, e);
3404    }
3405
3406    #[simd_test(enable = "avx512f,avx512vl")]
3407    unsafe fn test_mm256_getmant_pd() {
3408        let a = _mm256_set1_pd(10.);
3409        let r = _mm256_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3410        let e = _mm256_set1_pd(1.25);
3411        assert_eq_m256d(r, e);
3412    }
3413
3414    #[simd_test(enable = "avx512f,avx512vl")]
3415    unsafe fn test_mm256_mask_getmant_pd() {
3416        let a = _mm256_set1_pd(10.);
3417        let r = _mm256_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3418        assert_eq_m256d(r, a);
3419        let r = _mm256_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b00001111, a);
3420        let e = _mm256_set1_pd(1.25);
3421        assert_eq_m256d(r, e);
3422    }
3423
3424    #[simd_test(enable = "avx512f,avx512vl")]
3425    unsafe fn test_mm256_maskz_getmant_pd() {
3426        let a = _mm256_set1_pd(10.);
3427        let r = _mm256_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3428        assert_eq_m256d(r, _mm256_setzero_pd());
3429        let r = _mm256_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b00001111, a);
3430        let e = _mm256_set1_pd(1.25);
3431        assert_eq_m256d(r, e);
3432    }
3433
3434    #[simd_test(enable = "avx512f,avx512vl")]
3435    unsafe fn test_mm_getmant_pd() {
3436        let a = _mm_set1_pd(10.);
3437        let r = _mm_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3438        let e = _mm_set1_pd(1.25);
3439        assert_eq_m128d(r, e);
3440    }
3441
3442    #[simd_test(enable = "avx512f,avx512vl")]
3443    unsafe fn test_mm_mask_getmant_pd() {
3444        let a = _mm_set1_pd(10.);
3445        let r = _mm_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3446        assert_eq_m128d(r, a);
3447        let r = _mm_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b00000011, a);
3448        let e = _mm_set1_pd(1.25);
3449        assert_eq_m128d(r, e);
3450    }
3451
3452    #[simd_test(enable = "avx512f,avx512vl")]
3453    unsafe fn test_mm_maskz_getmant_pd() {
3454        let a = _mm_set1_pd(10.);
3455        let r = _mm_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3456        assert_eq_m128d(r, _mm_setzero_pd());
3457        let r = _mm_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b00000011, a);
3458        let e = _mm_set1_pd(1.25);
3459        assert_eq_m128d(r, e);
3460    }
3461
3462    #[simd_test(enable = "avx512f")]
3463    unsafe fn test_mm512_cvtps_pd() {
3464        let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3465        let r = _mm512_cvtps_pd(a);
3466        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3467        assert_eq_m512d(r, e);
3468    }
3469
3470    #[simd_test(enable = "avx512f")]
3471    unsafe fn test_mm512_mask_cvtps_pd() {
3472        let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3473        let src = _mm512_set1_pd(0.);
3474        let r = _mm512_mask_cvtps_pd(src, 0, a);
3475        assert_eq_m512d(r, src);
3476        let r = _mm512_mask_cvtps_pd(src, 0b00001111, a);
3477        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3478        assert_eq_m512d(r, e);
3479    }
3480
3481    #[simd_test(enable = "avx512f")]
3482    unsafe fn test_mm512_maskz_cvtps_pd() {
3483        let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3484        let r = _mm512_maskz_cvtps_pd(0, a);
3485        assert_eq_m512d(r, _mm512_setzero_pd());
3486        let r = _mm512_maskz_cvtps_pd(0b00001111, a);
3487        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3488        assert_eq_m512d(r, e);
3489    }
3490
3491    #[simd_test(enable = "avx512f")]
3492    unsafe fn test_mm512_cvtpslo_pd() {
3493        let v2 = _mm512_setr_ps(
3494            0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 100., 100., 100., 100., 100., 100., 100., 100.,
3495        );
3496        let r = _mm512_cvtpslo_pd(v2);
3497        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3498        assert_eq_m512d(r, e);
3499    }
3500
3501    #[simd_test(enable = "avx512f")]
3502    unsafe fn test_mm512_mask_cvtpslo_pd() {
3503        let v2 = _mm512_setr_ps(
3504            0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 100., 100., 100., 100., 100., 100., 100., 100.,
3505        );
3506        let src = _mm512_set1_pd(0.);
3507        let r = _mm512_mask_cvtpslo_pd(src, 0, v2);
3508        assert_eq_m512d(r, src);
3509        let r = _mm512_mask_cvtpslo_pd(src, 0b00001111, v2);
3510        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3511        assert_eq_m512d(r, e);
3512    }
3513
3514    #[simd_test(enable = "avx512f")]
3515    unsafe fn test_mm512_cvtpd_ps() {
3516        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3517        let r = _mm512_cvtpd_ps(a);
3518        let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3519        assert_eq_m256(r, e);
3520    }
3521
3522    #[simd_test(enable = "avx512f")]
3523    unsafe fn test_mm512_mask_cvtpd_ps() {
3524        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3525        let src = _mm256_set1_ps(0.);
3526        let r = _mm512_mask_cvtpd_ps(src, 0, a);
3527        assert_eq_m256(r, src);
3528        let r = _mm512_mask_cvtpd_ps(src, 0b00001111, a);
3529        let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3530        assert_eq_m256(r, e);
3531    }
3532
3533    #[simd_test(enable = "avx512f")]
3534    unsafe fn test_mm512_maskz_cvtpd_ps() {
3535        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3536        let r = _mm512_maskz_cvtpd_ps(0, a);
3537        assert_eq_m256(r, _mm256_setzero_ps());
3538        let r = _mm512_maskz_cvtpd_ps(0b00001111, a);
3539        let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3540        assert_eq_m256(r, e);
3541    }
3542
3543    #[simd_test(enable = "avx512f,avx512vl")]
3544    unsafe fn test_mm256_mask_cvtpd_ps() {
3545        let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3546        let src = _mm_set1_ps(0.);
3547        let r = _mm256_mask_cvtpd_ps(src, 0, a);
3548        assert_eq_m128(r, src);
3549        let r = _mm256_mask_cvtpd_ps(src, 0b00001111, a);
3550        let e = _mm_set_ps(4., -5.5, 6., -7.5);
3551        assert_eq_m128(r, e);
3552    }
3553
3554    #[simd_test(enable = "avx512f,avx512vl")]
3555    unsafe fn test_mm256_maskz_cvtpd_ps() {
3556        let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3557        let r = _mm256_maskz_cvtpd_ps(0, a);
3558        assert_eq_m128(r, _mm_setzero_ps());
3559        let r = _mm256_maskz_cvtpd_ps(0b00001111, a);
3560        let e = _mm_set_ps(4., -5.5, 6., -7.5);
3561        assert_eq_m128(r, e);
3562    }
3563
3564    #[simd_test(enable = "avx512f,avx512vl")]
3565    unsafe fn test_mm_mask_cvtpd_ps() {
3566        let a = _mm_set_pd(6., -7.5);
3567        let src = _mm_set1_ps(0.);
3568        let r = _mm_mask_cvtpd_ps(src, 0, a);
3569        assert_eq_m128(r, src);
3570        let r = _mm_mask_cvtpd_ps(src, 0b00000011, a);
3571        let e = _mm_set_ps(0., 0., 6., -7.5);
3572        assert_eq_m128(r, e);
3573    }
3574
3575    #[simd_test(enable = "avx512f,avx512vl")]
3576    unsafe fn test_mm_maskz_cvtpd_ps() {
3577        let a = _mm_set_pd(6., -7.5);
3578        let r = _mm_maskz_cvtpd_ps(0, a);
3579        assert_eq_m128(r, _mm_setzero_ps());
3580        let r = _mm_maskz_cvtpd_ps(0b00000011, a);
3581        let e = _mm_set_ps(0., 0., 6., -7.5);
3582        assert_eq_m128(r, e);
3583    }
3584
3585    #[simd_test(enable = "avx512f")]
3586    unsafe fn test_mm512_cvtpd_epi32() {
3587        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3588        let r = _mm512_cvtpd_epi32(a);
3589        let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3590        assert_eq_m256i(r, e);
3591    }
3592
3593    #[simd_test(enable = "avx512f")]
3594    unsafe fn test_mm512_mask_cvtpd_epi32() {
3595        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3596        let src = _mm256_set1_epi32(0);
3597        let r = _mm512_mask_cvtpd_epi32(src, 0, a);
3598        assert_eq_m256i(r, src);
3599        let r = _mm512_mask_cvtpd_epi32(src, 0b11111111, a);
3600        let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3601        assert_eq_m256i(r, e);
3602    }
3603
3604    #[simd_test(enable = "avx512f")]
3605    unsafe fn test_mm512_maskz_cvtpd_epi32() {
3606        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3607        let r = _mm512_maskz_cvtpd_epi32(0, a);
3608        assert_eq_m256i(r, _mm256_setzero_si256());
3609        let r = _mm512_maskz_cvtpd_epi32(0b11111111, a);
3610        let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3611        assert_eq_m256i(r, e);
3612    }
3613
3614    #[simd_test(enable = "avx512f,avx512vl")]
3615    unsafe fn test_mm256_mask_cvtpd_epi32() {
3616        let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3617        let src = _mm_set1_epi32(0);
3618        let r = _mm256_mask_cvtpd_epi32(src, 0, a);
3619        assert_eq_m128i(r, src);
3620        let r = _mm256_mask_cvtpd_epi32(src, 0b00001111, a);
3621        let e = _mm_set_epi32(4, -6, 6, -8);
3622        assert_eq_m128i(r, e);
3623    }
3624
3625    #[simd_test(enable = "avx512f,avx512vl")]
3626    unsafe fn test_mm256_maskz_cvtpd_epi32() {
3627        let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3628        let r = _mm256_maskz_cvtpd_epi32(0, a);
3629        assert_eq_m128i(r, _mm_setzero_si128());
3630        let r = _mm256_maskz_cvtpd_epi32(0b00001111, a);
3631        let e = _mm_set_epi32(4, -6, 6, -8);
3632        assert_eq_m128i(r, e);
3633    }
3634
3635    #[simd_test(enable = "avx512f,avx512vl")]
3636    unsafe fn test_mm_mask_cvtpd_epi32() {
3637        let a = _mm_set_pd(6., -7.5);
3638        let src = _mm_set1_epi32(0);
3639        let r = _mm_mask_cvtpd_epi32(src, 0, a);
3640        assert_eq_m128i(r, src);
3641        let r = _mm_mask_cvtpd_epi32(src, 0b00000011, a);
3642        let e = _mm_set_epi32(0, 0, 6, -8);
3643        assert_eq_m128i(r, e);
3644    }
3645
3646    #[simd_test(enable = "avx512f,avx512vl")]
3647    unsafe fn test_mm_maskz_cvtpd_epi32() {
3648        let a = _mm_set_pd(6., -7.5);
3649        let r = _mm_maskz_cvtpd_epi32(0, a);
3650        assert_eq_m128i(r, _mm_setzero_si128());
3651        let r = _mm_maskz_cvtpd_epi32(0b00000011, a);
3652        let e = _mm_set_epi32(0, 0, 6, -8);
3653        assert_eq_m128i(r, e);
3654    }
3655
3656    #[simd_test(enable = "avx512f")]
3657    unsafe fn test_mm512_cvtpd_epu32() {
3658        let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3659        let r = _mm512_cvtpd_epu32(a);
3660        let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3661        assert_eq_m256i(r, e);
3662    }
3663
3664    #[simd_test(enable = "avx512f")]
3665    unsafe fn test_mm512_mask_cvtpd_epu32() {
3666        let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3667        let src = _mm256_set1_epi32(0);
3668        let r = _mm512_mask_cvtpd_epu32(src, 0, a);
3669        assert_eq_m256i(r, src);
3670        let r = _mm512_mask_cvtpd_epu32(src, 0b11111111, a);
3671        let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3672        assert_eq_m256i(r, e);
3673    }
3674
3675    #[simd_test(enable = "avx512f")]
3676    unsafe fn test_mm512_maskz_cvtpd_epu32() {
3677        let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3678        let r = _mm512_maskz_cvtpd_epu32(0, a);
3679        assert_eq_m256i(r, _mm256_setzero_si256());
3680        let r = _mm512_maskz_cvtpd_epu32(0b11111111, a);
3681        let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3682        assert_eq_m256i(r, e);
3683    }
3684
3685    #[simd_test(enable = "avx512f,avx512vl")]
3686    unsafe fn test_mm256_cvtpd_epu32() {
3687        let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3688        let r = _mm256_cvtpd_epu32(a);
3689        let e = _mm_set_epi32(4, 6, 6, 8);
3690        assert_eq_m128i(r, e);
3691    }
3692
3693    #[simd_test(enable = "avx512f,avx512vl")]
3694    unsafe fn test_mm256_mask_cvtpd_epu32() {
3695        let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3696        let src = _mm_set1_epi32(0);
3697        let r = _mm256_mask_cvtpd_epu32(src, 0, a);
3698        assert_eq_m128i(r, src);
3699        let r = _mm256_mask_cvtpd_epu32(src, 0b00001111, a);
3700        let e = _mm_set_epi32(4, 6, 6, 8);
3701        assert_eq_m128i(r, e);
3702    }
3703
3704    #[simd_test(enable = "avx512f,avx512vl")]
3705    unsafe fn test_mm256_maskz_cvtpd_epu32() {
3706        let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3707        let r = _mm256_maskz_cvtpd_epu32(0, a);
3708        assert_eq_m128i(r, _mm_setzero_si128());
3709        let r = _mm256_maskz_cvtpd_epu32(0b00001111, a);
3710        let e = _mm_set_epi32(4, 6, 6, 8);
3711        assert_eq_m128i(r, e);
3712    }
3713
3714    #[simd_test(enable = "avx512f,avx512vl")]
3715    unsafe fn test_mm_cvtpd_epu32() {
3716        let a = _mm_set_pd(6., 7.5);
3717        let r = _mm_cvtpd_epu32(a);
3718        let e = _mm_set_epi32(0, 0, 6, 8);
3719        assert_eq_m128i(r, e);
3720    }
3721
3722    #[simd_test(enable = "avx512f,avx512vl")]
3723    unsafe fn test_mm_mask_cvtpd_epu32() {
3724        let a = _mm_set_pd(6., 7.5);
3725        let src = _mm_set1_epi32(0);
3726        let r = _mm_mask_cvtpd_epu32(src, 0, a);
3727        assert_eq_m128i(r, src);
3728        let r = _mm_mask_cvtpd_epu32(src, 0b00000011, a);
3729        let e = _mm_set_epi32(0, 0, 6, 8);
3730        assert_eq_m128i(r, e);
3731    }
3732
3733    #[simd_test(enable = "avx512f,avx512vl")]
3734    unsafe fn test_mm_maskz_cvtpd_epu32() {
3735        let a = _mm_set_pd(6., 7.5);
3736        let r = _mm_maskz_cvtpd_epu32(0, a);
3737        assert_eq_m128i(r, _mm_setzero_si128());
3738        let r = _mm_maskz_cvtpd_epu32(0b00000011, a);
3739        let e = _mm_set_epi32(0, 0, 6, 8);
3740        assert_eq_m128i(r, e);
3741    }
3742
3743    #[simd_test(enable = "avx512f")]
3744    unsafe fn test_mm512_cvtpd_pslo() {
3745        let v2 = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3746        let r = _mm512_cvtpd_pslo(v2);
3747        let e = _mm512_setr_ps(
3748            0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 0., 0., 0., 0., 0., 0., 0., 0.,
3749        );
3750        assert_eq_m512(r, e);
3751    }
3752
3753    #[simd_test(enable = "avx512f")]
3754    unsafe fn test_mm512_mask_cvtpd_pslo() {
3755        let v2 = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3756        let src = _mm512_set1_ps(0.);
3757        let r = _mm512_mask_cvtpd_pslo(src, 0, v2);
3758        assert_eq_m512(r, src);
3759        let r = _mm512_mask_cvtpd_pslo(src, 0b00001111, v2);
3760        let e = _mm512_setr_ps(
3761            0., -1.5, 2., -3.5, 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0.,
3762        );
3763        assert_eq_m512(r, e);
3764    }
3765
3766    #[simd_test(enable = "avx512f")]
3767    unsafe fn test_mm512_cvtepi8_epi64() {
3768        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3769        let r = _mm512_cvtepi8_epi64(a);
3770        let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3771        assert_eq_m512i(r, e);
3772    }
3773
3774    #[simd_test(enable = "avx512f")]
3775    unsafe fn test_mm512_mask_cvtepi8_epi64() {
3776        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3777        let src = _mm512_set1_epi64(-1);
3778        let r = _mm512_mask_cvtepi8_epi64(src, 0, a);
3779        assert_eq_m512i(r, src);
3780        let r = _mm512_mask_cvtepi8_epi64(src, 0b00001111, a);
3781        let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3782        assert_eq_m512i(r, e);
3783    }
3784
3785    #[simd_test(enable = "avx512f")]
3786    unsafe fn test_mm512_maskz_cvtepi8_epi64() {
3787        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3788        let r = _mm512_maskz_cvtepi8_epi64(0, a);
3789        assert_eq_m512i(r, _mm512_setzero_si512());
3790        let r = _mm512_maskz_cvtepi8_epi64(0b00001111, a);
3791        let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3792        assert_eq_m512i(r, e);
3793    }
3794
3795    #[simd_test(enable = "avx512f,avx512vl")]
3796    unsafe fn test_mm256_mask_cvtepi8_epi64() {
3797        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3798        let src = _mm256_set1_epi64x(-1);
3799        let r = _mm256_mask_cvtepi8_epi64(src, 0, a);
3800        assert_eq_m256i(r, src);
3801        let r = _mm256_mask_cvtepi8_epi64(src, 0b00001111, a);
3802        let e = _mm256_set_epi64x(12, 13, 14, 15);
3803        assert_eq_m256i(r, e);
3804    }
3805
3806    #[simd_test(enable = "avx512f,avx512vl")]
3807    unsafe fn test_mm256_maskz_cvtepi8_epi64() {
3808        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3809        let r = _mm256_maskz_cvtepi8_epi64(0, a);
3810        assert_eq_m256i(r, _mm256_setzero_si256());
3811        let r = _mm256_maskz_cvtepi8_epi64(0b00001111, a);
3812        let e = _mm256_set_epi64x(12, 13, 14, 15);
3813        assert_eq_m256i(r, e);
3814    }
3815
3816    #[simd_test(enable = "avx512f,avx512vl")]
3817    unsafe fn test_mm_mask_cvtepi8_epi64() {
3818        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3819        let src = _mm_set1_epi64x(-1);
3820        let r = _mm_mask_cvtepi8_epi64(src, 0, a);
3821        assert_eq_m128i(r, src);
3822        let r = _mm_mask_cvtepi8_epi64(src, 0b00000011, a);
3823        let e = _mm_set_epi64x(14, 15);
3824        assert_eq_m128i(r, e);
3825    }
3826
3827    #[simd_test(enable = "avx512f,avx512vl")]
3828    unsafe fn test_mm_maskz_cvtepi8_epi64() {
3829        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3830        let r = _mm_maskz_cvtepi8_epi64(0, a);
3831        assert_eq_m128i(r, _mm_setzero_si128());
3832        let r = _mm_maskz_cvtepi8_epi64(0b00000011, a);
3833        let e = _mm_set_epi64x(14, 15);
3834        assert_eq_m128i(r, e);
3835    }
3836
3837    #[simd_test(enable = "avx512f")]
3838    unsafe fn test_mm512_cvtepu8_epi64() {
3839        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3840        let r = _mm512_cvtepu8_epi64(a);
3841        let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3842        assert_eq_m512i(r, e);
3843    }
3844
3845    #[simd_test(enable = "avx512f")]
3846    unsafe fn test_mm512_mask_cvtepu8_epi64() {
3847        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3848        let src = _mm512_set1_epi64(-1);
3849        let r = _mm512_mask_cvtepu8_epi64(src, 0, a);
3850        assert_eq_m512i(r, src);
3851        let r = _mm512_mask_cvtepu8_epi64(src, 0b00001111, a);
3852        let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3853        assert_eq_m512i(r, e);
3854    }
3855
3856    #[simd_test(enable = "avx512f")]
3857    unsafe fn test_mm512_maskz_cvtepu8_epi64() {
3858        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3859        let r = _mm512_maskz_cvtepu8_epi64(0, a);
3860        assert_eq_m512i(r, _mm512_setzero_si512());
3861        let r = _mm512_maskz_cvtepu8_epi64(0b00001111, a);
3862        let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3863        assert_eq_m512i(r, e);
3864    }
3865
3866    #[simd_test(enable = "avx512f,avx512vl")]
3867    unsafe fn test_mm256_mask_cvtepu8_epi64() {
3868        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3869        let src = _mm256_set1_epi64x(-1);
3870        let r = _mm256_mask_cvtepu8_epi64(src, 0, a);
3871        assert_eq_m256i(r, src);
3872        let r = _mm256_mask_cvtepu8_epi64(src, 0b00001111, a);
3873        let e = _mm256_set_epi64x(12, 13, 14, 15);
3874        assert_eq_m256i(r, e);
3875    }
3876
3877    #[simd_test(enable = "avx512f,avx512vl")]
3878    unsafe fn test_mm256_maskz_cvtepu8_epi64() {
3879        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3880        let r = _mm256_maskz_cvtepu8_epi64(0, a);
3881        assert_eq_m256i(r, _mm256_setzero_si256());
3882        let r = _mm256_maskz_cvtepu8_epi64(0b00001111, a);
3883        let e = _mm256_set_epi64x(12, 13, 14, 15);
3884        assert_eq_m256i(r, e);
3885    }
3886
3887    #[simd_test(enable = "avx512f,avx512vl")]
3888    unsafe fn test_mm_mask_cvtepu8_epi64() {
3889        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3890        let src = _mm_set1_epi64x(-1);
3891        let r = _mm_mask_cvtepu8_epi64(src, 0, a);
3892        assert_eq_m128i(r, src);
3893        let r = _mm_mask_cvtepu8_epi64(src, 0b00000011, a);
3894        let e = _mm_set_epi64x(14, 15);
3895        assert_eq_m128i(r, e);
3896    }
3897
3898    #[simd_test(enable = "avx512f,avx512vl")]
3899    unsafe fn test_mm_maskz_cvtepu8_epi64() {
3900        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3901        let r = _mm_maskz_cvtepu8_epi64(0, a);
3902        assert_eq_m128i(r, _mm_setzero_si128());
3903        let r = _mm_maskz_cvtepu8_epi64(0b00000011, a);
3904        let e = _mm_set_epi64x(14, 15);
3905        assert_eq_m128i(r, e);
3906    }
3907
3908    #[simd_test(enable = "avx512f")]
3909    unsafe fn test_mm512_cvtepi16_epi64() {
3910        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3911        let r = _mm512_cvtepi16_epi64(a);
3912        let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3913        assert_eq_m512i(r, e);
3914    }
3915
3916    #[simd_test(enable = "avx512f")]
3917    unsafe fn test_mm512_mask_cvtepi16_epi64() {
3918        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3919        let src = _mm512_set1_epi64(-1);
3920        let r = _mm512_mask_cvtepi16_epi64(src, 0, a);
3921        assert_eq_m512i(r, src);
3922        let r = _mm512_mask_cvtepi16_epi64(src, 0b00001111, a);
3923        let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3924        assert_eq_m512i(r, e);
3925    }
3926
3927    #[simd_test(enable = "avx512f")]
3928    unsafe fn test_mm512_maskz_cvtepi16_epi64() {
3929        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3930        let r = _mm512_maskz_cvtepi16_epi64(0, a);
3931        assert_eq_m512i(r, _mm512_setzero_si512());
3932        let r = _mm512_maskz_cvtepi16_epi64(0b00001111, a);
3933        let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3934        assert_eq_m512i(r, e);
3935    }
3936
3937    #[simd_test(enable = "avx512f,avx512vl")]
3938    unsafe fn test_mm256_mask_cvtepi16_epi64() {
3939        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3940        let src = _mm256_set1_epi64x(-1);
3941        let r = _mm256_mask_cvtepi16_epi64(src, 0, a);
3942        assert_eq_m256i(r, src);
3943        let r = _mm256_mask_cvtepi16_epi64(src, 0b00001111, a);
3944        let e = _mm256_set_epi64x(12, 13, 14, 15);
3945        assert_eq_m256i(r, e);
3946    }
3947
3948    #[simd_test(enable = "avx512f,avx512vl")]
3949    unsafe fn test_mm256_maskz_cvtepi16_epi64() {
3950        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3951        let r = _mm256_maskz_cvtepi16_epi64(0, a);
3952        assert_eq_m256i(r, _mm256_setzero_si256());
3953        let r = _mm256_maskz_cvtepi16_epi64(0b00001111, a);
3954        let e = _mm256_set_epi64x(12, 13, 14, 15);
3955        assert_eq_m256i(r, e);
3956    }
3957
3958    #[simd_test(enable = "avx512f,avx512vl")]
3959    unsafe fn test_mm_mask_cvtepi16_epi64() {
3960        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3961        let src = _mm_set1_epi64x(-1);
3962        let r = _mm_mask_cvtepi16_epi64(src, 0, a);
3963        assert_eq_m128i(r, src);
3964        let r = _mm_mask_cvtepi16_epi64(src, 0b00000011, a);
3965        let e = _mm_set_epi64x(14, 15);
3966        assert_eq_m128i(r, e);
3967    }
3968
3969    #[simd_test(enable = "avx512f,avx512vl")]
3970    unsafe fn test_mm_maskz_cvtepi16_epi64() {
3971        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3972        let r = _mm_maskz_cvtepi16_epi64(0, a);
3973        assert_eq_m128i(r, _mm_setzero_si128());
3974        let r = _mm_maskz_cvtepi16_epi64(0b00000011, a);
3975        let e = _mm_set_epi64x(14, 15);
3976        assert_eq_m128i(r, e);
3977    }
3978
3979    #[simd_test(enable = "avx512f")]
3980    unsafe fn test_mm512_cvtepu16_epi64() {
3981        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3982        let r = _mm512_cvtepu16_epi64(a);
3983        let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3984        assert_eq_m512i(r, e);
3985    }
3986
3987    #[simd_test(enable = "avx512f")]
3988    unsafe fn test_mm512_mask_cvtepu16_epi64() {
3989        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3990        let src = _mm512_set1_epi64(-1);
3991        let r = _mm512_mask_cvtepu16_epi64(src, 0, a);
3992        assert_eq_m512i(r, src);
3993        let r = _mm512_mask_cvtepu16_epi64(src, 0b00001111, a);
3994        let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3995        assert_eq_m512i(r, e);
3996    }
3997
3998    #[simd_test(enable = "avx512f")]
3999    unsafe fn test_mm512_maskz_cvtepu16_epi64() {
4000        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4001        let r = _mm512_maskz_cvtepu16_epi64(0, a);
4002        assert_eq_m512i(r, _mm512_setzero_si512());
4003        let r = _mm512_maskz_cvtepu16_epi64(0b00001111, a);
4004        let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
4005        assert_eq_m512i(r, e);
4006    }
4007
4008    #[simd_test(enable = "avx512f,avx512vl")]
4009    unsafe fn test_mm256_mask_cvtepu16_epi64() {
4010        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4011        let src = _mm256_set1_epi64x(-1);
4012        let r = _mm256_mask_cvtepu16_epi64(src, 0, a);
4013        assert_eq_m256i(r, src);
4014        let r = _mm256_mask_cvtepu16_epi64(src, 0b00001111, a);
4015        let e = _mm256_set_epi64x(12, 13, 14, 15);
4016        assert_eq_m256i(r, e);
4017    }
4018
4019    #[simd_test(enable = "avx512f,avx512vl")]
4020    unsafe fn test_mm256_maskz_cvtepu16_epi64() {
4021        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4022        let r = _mm256_maskz_cvtepu16_epi64(0, a);
4023        assert_eq_m256i(r, _mm256_setzero_si256());
4024        let r = _mm256_maskz_cvtepu16_epi64(0b00001111, a);
4025        let e = _mm256_set_epi64x(12, 13, 14, 15);
4026        assert_eq_m256i(r, e);
4027    }
4028
4029    #[simd_test(enable = "avx512f,avx512vl")]
4030    unsafe fn test_mm_mask_cvtepu16_epi64() {
4031        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4032        let src = _mm_set1_epi64x(-1);
4033        let r = _mm_mask_cvtepu16_epi64(src, 0, a);
4034        assert_eq_m128i(r, src);
4035        let r = _mm_mask_cvtepu16_epi64(src, 0b00000011, a);
4036        let e = _mm_set_epi64x(14, 15);
4037        assert_eq_m128i(r, e);
4038    }
4039
4040    #[simd_test(enable = "avx512f,avx512vl")]
4041    unsafe fn test_mm_maskz_cvtepu16_epi64() {
4042        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4043        let r = _mm_maskz_cvtepu16_epi64(0, a);
4044        assert_eq_m128i(r, _mm_setzero_si128());
4045        let r = _mm_maskz_cvtepu16_epi64(0b00000011, a);
4046        let e = _mm_set_epi64x(14, 15);
4047        assert_eq_m128i(r, e);
4048    }
4049
4050    #[simd_test(enable = "avx512f")]
4051    unsafe fn test_mm512_cvtepi32_epi64() {
4052        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4053        let r = _mm512_cvtepi32_epi64(a);
4054        let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4055        assert_eq_m512i(r, e);
4056    }
4057
4058    #[simd_test(enable = "avx512f")]
4059    unsafe fn test_mm512_mask_cvtepi32_epi64() {
4060        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4061        let src = _mm512_set1_epi64(-1);
4062        let r = _mm512_mask_cvtepi32_epi64(src, 0, a);
4063        assert_eq_m512i(r, src);
4064        let r = _mm512_mask_cvtepi32_epi64(src, 0b00001111, a);
4065        let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
4066        assert_eq_m512i(r, e);
4067    }
4068
4069    #[simd_test(enable = "avx512f")]
4070    unsafe fn test_mm512_maskz_cvtepi32_epi64() {
4071        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4072        let r = _mm512_maskz_cvtepi32_epi64(0, a);
4073        assert_eq_m512i(r, _mm512_setzero_si512());
4074        let r = _mm512_maskz_cvtepi32_epi64(0b00001111, a);
4075        let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
4076        assert_eq_m512i(r, e);
4077    }
4078
4079    #[simd_test(enable = "avx512f,avx512vl")]
4080    unsafe fn test_mm256_mask_cvtepi32_epi64() {
4081        let a = _mm_set_epi32(8, 9, 10, 11);
4082        let src = _mm256_set1_epi64x(-1);
4083        let r = _mm256_mask_cvtepi32_epi64(src, 0, a);
4084        assert_eq_m256i(r, src);
4085        let r = _mm256_mask_cvtepi32_epi64(src, 0b00001111, a);
4086        let e = _mm256_set_epi64x(8, 9, 10, 11);
4087        assert_eq_m256i(r, e);
4088    }
4089
4090    #[simd_test(enable = "avx512f,avx512vl")]
4091    unsafe fn test_mm256_maskz_cvtepi32_epi64() {
4092        let a = _mm_set_epi32(8, 9, 10, 11);
4093        let r = _mm256_maskz_cvtepi32_epi64(0, a);
4094        assert_eq_m256i(r, _mm256_setzero_si256());
4095        let r = _mm256_maskz_cvtepi32_epi64(0b00001111, a);
4096        let e = _mm256_set_epi64x(8, 9, 10, 11);
4097        assert_eq_m256i(r, e);
4098    }
4099
4100    #[simd_test(enable = "avx512f,avx512vl")]
4101    unsafe fn test_mm_mask_cvtepi32_epi64() {
4102        let a = _mm_set_epi32(8, 9, 10, 11);
4103        let src = _mm_set1_epi64x(0);
4104        let r = _mm_mask_cvtepi32_epi64(src, 0, a);
4105        assert_eq_m128i(r, src);
4106        let r = _mm_mask_cvtepi32_epi64(src, 0b00000011, a);
4107        let e = _mm_set_epi64x(10, 11);
4108        assert_eq_m128i(r, e);
4109    }
4110
4111    #[simd_test(enable = "avx512f,avx512vl")]
4112    unsafe fn test_mm_maskz_cvtepi32_epi64() {
4113        let a = _mm_set_epi32(8, 9, 10, 11);
4114        let r = _mm_maskz_cvtepi32_epi64(0, a);
4115        assert_eq_m128i(r, _mm_setzero_si128());
4116        let r = _mm_maskz_cvtepi32_epi64(0b00000011, a);
4117        let e = _mm_set_epi64x(10, 11);
4118        assert_eq_m128i(r, e);
4119    }
4120
4121    #[simd_test(enable = "avx512f")]
4122    unsafe fn test_mm512_cvtepu32_epi64() {
4123        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4124        let r = _mm512_cvtepu32_epi64(a);
4125        let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4126        assert_eq_m512i(r, e);
4127    }
4128
4129    #[simd_test(enable = "avx512f")]
4130    unsafe fn test_mm512_mask_cvtepu32_epi64() {
4131        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4132        let src = _mm512_set1_epi64(-1);
4133        let r = _mm512_mask_cvtepu32_epi64(src, 0, a);
4134        assert_eq_m512i(r, src);
4135        let r = _mm512_mask_cvtepu32_epi64(src, 0b00001111, a);
4136        let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
4137        assert_eq_m512i(r, e);
4138    }
4139
4140    #[simd_test(enable = "avx512f")]
4141    unsafe fn test_mm512_maskz_cvtepu32_epi64() {
4142        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4143        let r = _mm512_maskz_cvtepu32_epi64(0, a);
4144        assert_eq_m512i(r, _mm512_setzero_si512());
4145        let r = _mm512_maskz_cvtepu32_epi64(0b00001111, a);
4146        let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
4147        assert_eq_m512i(r, e);
4148    }
4149
4150    #[simd_test(enable = "avx512f,avx512vl")]
4151    unsafe fn test_mm256_mask_cvtepu32_epi64() {
4152        let a = _mm_set_epi32(12, 13, 14, 15);
4153        let src = _mm256_set1_epi64x(-1);
4154        let r = _mm256_mask_cvtepu32_epi64(src, 0, a);
4155        assert_eq_m256i(r, src);
4156        let r = _mm256_mask_cvtepu32_epi64(src, 0b00001111, a);
4157        let e = _mm256_set_epi64x(12, 13, 14, 15);
4158        assert_eq_m256i(r, e);
4159    }
4160
4161    #[simd_test(enable = "avx512f,avx512vl")]
4162    unsafe fn test_mm256_maskz_cvtepu32_epi64() {
4163        let a = _mm_set_epi32(12, 13, 14, 15);
4164        let r = _mm256_maskz_cvtepu32_epi64(0, a);
4165        assert_eq_m256i(r, _mm256_setzero_si256());
4166        let r = _mm256_maskz_cvtepu32_epi64(0b00001111, a);
4167        let e = _mm256_set_epi64x(12, 13, 14, 15);
4168        assert_eq_m256i(r, e);
4169    }
4170
4171    #[simd_test(enable = "avx512f,avx512vl")]
4172    unsafe fn test_mm_mask_cvtepu32_epi64() {
4173        let a = _mm_set_epi32(12, 13, 14, 15);
4174        let src = _mm_set1_epi64x(-1);
4175        let r = _mm_mask_cvtepu32_epi64(src, 0, a);
4176        assert_eq_m128i(r, src);
4177        let r = _mm_mask_cvtepu32_epi64(src, 0b00000011, a);
4178        let e = _mm_set_epi64x(14, 15);
4179        assert_eq_m128i(r, e);
4180    }
4181
4182    #[simd_test(enable = "avx512f,avx512vl")]
4183    unsafe fn test_mm_maskz_cvtepu32_epi64() {
4184        let a = _mm_set_epi32(12, 13, 14, 15);
4185        let r = _mm_maskz_cvtepu32_epi64(0, a);
4186        assert_eq_m128i(r, _mm_setzero_si128());
4187        let r = _mm_maskz_cvtepu32_epi64(0b00000011, a);
4188        let e = _mm_set_epi64x(14, 15);
4189        assert_eq_m128i(r, e);
4190    }
4191
4192    #[simd_test(enable = "avx512f")]
4193    unsafe fn test_mm512_cvtepi32_pd() {
4194        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4195        let r = _mm512_cvtepi32_pd(a);
4196        let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4197        assert_eq_m512d(r, e);
4198    }
4199
4200    #[simd_test(enable = "avx512f")]
4201    unsafe fn test_mm512_mask_cvtepi32_pd() {
4202        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4203        let src = _mm512_set1_pd(-1.);
4204        let r = _mm512_mask_cvtepi32_pd(src, 0, a);
4205        assert_eq_m512d(r, src);
4206        let r = _mm512_mask_cvtepi32_pd(src, 0b00001111, a);
4207        let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4208        assert_eq_m512d(r, e);
4209    }
4210
4211    #[simd_test(enable = "avx512f")]
4212    unsafe fn test_mm512_maskz_cvtepi32_pd() {
4213        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4214        let r = _mm512_maskz_cvtepi32_pd(0, a);
4215        assert_eq_m512d(r, _mm512_setzero_pd());
4216        let r = _mm512_maskz_cvtepi32_pd(0b00001111, a);
4217        let e = _mm512_set_pd(0., 0., 0., 0., 12., 13., 14., 15.);
4218        assert_eq_m512d(r, e);
4219    }
4220
4221    #[simd_test(enable = "avx512f,avx512vl")]
4222    unsafe fn test_mm256_mask_cvtepi32_pd() {
4223        let a = _mm_set_epi32(12, 13, 14, 15);
4224        let src = _mm256_set1_pd(-1.);
4225        let r = _mm256_mask_cvtepi32_pd(src, 0, a);
4226        assert_eq_m256d(r, src);
4227        let r = _mm256_mask_cvtepi32_pd(src, 0b00001111, a);
4228        let e = _mm256_set_pd(12., 13., 14., 15.);
4229        assert_eq_m256d(r, e);
4230    }
4231
4232    #[simd_test(enable = "avx512f,avx512vl")]
4233    unsafe fn test_mm256_maskz_cvtepi32_pd() {
4234        let a = _mm_set_epi32(12, 13, 14, 15);
4235        let r = _mm256_maskz_cvtepi32_pd(0, a);
4236        assert_eq_m256d(r, _mm256_setzero_pd());
4237        let r = _mm256_maskz_cvtepi32_pd(0b00001111, a);
4238        let e = _mm256_set_pd(12., 13., 14., 15.);
4239        assert_eq_m256d(r, e);
4240    }
4241
4242    #[simd_test(enable = "avx512f,avx512vl")]
4243    unsafe fn test_mm_mask_cvtepi32_pd() {
4244        let a = _mm_set_epi32(12, 13, 14, 15);
4245        let src = _mm_set1_pd(-1.);
4246        let r = _mm_mask_cvtepi32_pd(src, 0, a);
4247        assert_eq_m128d(r, src);
4248        let r = _mm_mask_cvtepi32_pd(src, 0b00000011, a);
4249        let e = _mm_set_pd(14., 15.);
4250        assert_eq_m128d(r, e);
4251    }
4252
4253    #[simd_test(enable = "avx512f,avx512vl")]
4254    unsafe fn test_mm_maskz_cvtepi32_pd() {
4255        let a = _mm_set_epi32(12, 13, 14, 15);
4256        let r = _mm_maskz_cvtepi32_pd(0, a);
4257        assert_eq_m128d(r, _mm_setzero_pd());
4258        let r = _mm_maskz_cvtepi32_pd(0b00000011, a);
4259        let e = _mm_set_pd(14., 15.);
4260        assert_eq_m128d(r, e);
4261    }
4262
4263    #[simd_test(enable = "avx512f")]
4264    unsafe fn test_mm512_cvtepu32_pd() {
4265        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4266        let r = _mm512_cvtepu32_pd(a);
4267        let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4268        assert_eq_m512d(r, e);
4269    }
4270
4271    #[simd_test(enable = "avx512f")]
4272    unsafe fn test_mm512_mask_cvtepu32_pd() {
4273        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4274        let src = _mm512_set1_pd(-1.);
4275        let r = _mm512_mask_cvtepu32_pd(src, 0, a);
4276        assert_eq_m512d(r, src);
4277        let r = _mm512_mask_cvtepu32_pd(src, 0b00001111, a);
4278        let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4279        assert_eq_m512d(r, e);
4280    }
4281
4282    #[simd_test(enable = "avx512f")]
4283    unsafe fn test_mm512_maskz_cvtepu32_pd() {
4284        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4285        let r = _mm512_maskz_cvtepu32_pd(0, a);
4286        assert_eq_m512d(r, _mm512_setzero_pd());
4287        let r = _mm512_maskz_cvtepu32_pd(0b00001111, a);
4288        let e = _mm512_set_pd(0., 0., 0., 0., 12., 13., 14., 15.);
4289        assert_eq_m512d(r, e);
4290    }
4291
4292    #[simd_test(enable = "avx512f,avx512vl")]
4293    unsafe fn test_mm256_cvtepu32_pd() {
4294        let a = _mm_set_epi32(12, 13, 14, 15);
4295        let r = _mm256_cvtepu32_pd(a);
4296        let e = _mm256_set_pd(12., 13., 14., 15.);
4297        assert_eq_m256d(r, e);
4298    }
4299
4300    #[simd_test(enable = "avx512f,avx512vl")]
4301    unsafe fn test_mm256_mask_cvtepu32_pd() {
4302        let a = _mm_set_epi32(12, 13, 14, 15);
4303        let src = _mm256_set1_pd(-1.);
4304        let r = _mm256_mask_cvtepu32_pd(src, 0, a);
4305        assert_eq_m256d(r, src);
4306        let r = _mm256_mask_cvtepu32_pd(src, 0b00001111, a);
4307        let e = _mm256_set_pd(12., 13., 14., 15.);
4308        assert_eq_m256d(r, e);
4309    }
4310
4311    #[simd_test(enable = "avx512f,avx512vl")]
4312    unsafe fn test_mm256_maskz_cvtepu32_pd() {
4313        let a = _mm_set_epi32(12, 13, 14, 15);
4314        let r = _mm256_maskz_cvtepu32_pd(0, a);
4315        assert_eq_m256d(r, _mm256_setzero_pd());
4316        let r = _mm256_maskz_cvtepu32_pd(0b00001111, a);
4317        let e = _mm256_set_pd(12., 13., 14., 15.);
4318        assert_eq_m256d(r, e);
4319    }
4320
4321    #[simd_test(enable = "avx512f,avx512vl")]
4322    unsafe fn test_mm_cvtepu32_pd() {
4323        let a = _mm_set_epi32(12, 13, 14, 15);
4324        let r = _mm_cvtepu32_pd(a);
4325        let e = _mm_set_pd(14., 15.);
4326        assert_eq_m128d(r, e);
4327    }
4328
4329    #[simd_test(enable = "avx512f,avx512vl")]
4330    unsafe fn test_mm_mask_cvtepu32_pd() {
4331        let a = _mm_set_epi32(12, 13, 14, 15);
4332        let src = _mm_set1_pd(-1.);
4333        let r = _mm_mask_cvtepu32_pd(src, 0, a);
4334        assert_eq_m128d(r, src);
4335        let r = _mm_mask_cvtepu32_pd(src, 0b00000011, a);
4336        let e = _mm_set_pd(14., 15.);
4337        assert_eq_m128d(r, e);
4338    }
4339
4340    #[simd_test(enable = "avx512f,avx512vl")]
4341    unsafe fn test_mm_maskz_cvtepu32_pd() {
4342        let a = _mm_set_epi32(12, 13, 14, 15);
4343        let r = _mm_maskz_cvtepu32_pd(0, a);
4344        assert_eq_m128d(r, _mm_setzero_pd());
4345        let r = _mm_maskz_cvtepu32_pd(0b00000011, a);
4346        let e = _mm_set_pd(14., 15.);
4347        assert_eq_m128d(r, e);
4348    }
4349
4350    #[simd_test(enable = "avx512f")]
4351    unsafe fn test_mm512_cvtepi32lo_pd() {
4352        let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4353        let r = _mm512_cvtepi32lo_pd(a);
4354        let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4355        assert_eq_m512d(r, e);
4356    }
4357
4358    #[simd_test(enable = "avx512f")]
4359    unsafe fn test_mm512_mask_cvtepi32lo_pd() {
4360        let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4361        let src = _mm512_set1_pd(-1.);
4362        let r = _mm512_mask_cvtepi32lo_pd(src, 0, a);
4363        assert_eq_m512d(r, src);
4364        let r = _mm512_mask_cvtepi32lo_pd(src, 0b00001111, a);
4365        let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4366        assert_eq_m512d(r, e);
4367    }
4368
4369    #[simd_test(enable = "avx512f")]
4370    unsafe fn test_mm512_cvtepu32lo_pd() {
4371        let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4372        let r = _mm512_cvtepu32lo_pd(a);
4373        let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4374        assert_eq_m512d(r, e);
4375    }
4376
4377    #[simd_test(enable = "avx512f")]
4378    unsafe fn test_mm512_mask_cvtepu32lo_pd() {
4379        let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4380        let src = _mm512_set1_pd(-1.);
4381        let r = _mm512_mask_cvtepu32lo_pd(src, 0, a);
4382        assert_eq_m512d(r, src);
4383        let r = _mm512_mask_cvtepu32lo_pd(src, 0b00001111, a);
4384        let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4385        assert_eq_m512d(r, e);
4386    }
4387
4388    #[simd_test(enable = "avx512f")]
4389    unsafe fn test_mm512_cvtepi64_epi32() {
4390        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4391        let r = _mm512_cvtepi64_epi32(a);
4392        let e = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4393        assert_eq_m256i(r, e);
4394    }
4395
4396    #[simd_test(enable = "avx512f")]
4397    unsafe fn test_mm512_mask_cvtepi64_epi32() {
4398        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4399        let src = _mm256_set1_epi32(-1);
4400        let r = _mm512_mask_cvtepi64_epi32(src, 0, a);
4401        assert_eq_m256i(r, src);
4402        let r = _mm512_mask_cvtepi64_epi32(src, 0b00001111, a);
4403        let e = _mm256_set_epi32(-1, -1, -1, -1, 12, 13, 14, 15);
4404        assert_eq_m256i(r, e);
4405    }
4406
4407    #[simd_test(enable = "avx512f")]
4408    unsafe fn test_mm512_maskz_cvtepi64_epi32() {
4409        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4410        let r = _mm512_maskz_cvtepi64_epi32(0, a);
4411        assert_eq_m256i(r, _mm256_setzero_si256());
4412        let r = _mm512_maskz_cvtepi64_epi32(0b00001111, a);
4413        let e = _mm256_set_epi32(0, 0, 0, 0, 12, 13, 14, 15);
4414        assert_eq_m256i(r, e);
4415    }
4416
4417    #[simd_test(enable = "avx512f,avx512vl")]
4418    unsafe fn test_mm256_cvtepi64_epi32() {
4419        let a = _mm256_set_epi64x(1, 2, 3, 4);
4420        let r = _mm256_cvtepi64_epi32(a);
4421        let e = _mm_set_epi32(1, 2, 3, 4);
4422        assert_eq_m128i(r, e);
4423    }
4424
4425    #[simd_test(enable = "avx512f,avx512vl")]
4426    unsafe fn test_mm256_mask_cvtepi64_epi32() {
4427        let a = _mm256_set_epi64x(1, 2, 3, 4);
4428        let src = _mm_set1_epi32(0);
4429        let r = _mm256_mask_cvtepi64_epi32(src, 0, a);
4430        assert_eq_m128i(r, src);
4431        let r = _mm256_mask_cvtepi64_epi32(src, 0b00001111, a);
4432        let e = _mm_set_epi32(1, 2, 3, 4);
4433        assert_eq_m128i(r, e);
4434    }
4435
4436    #[simd_test(enable = "avx512f,avx512vl")]
4437    unsafe fn test_mm256_maskz_cvtepi64_epi32() {
4438        let a = _mm256_set_epi64x(1, 2, 3, 4);
4439        let r = _mm256_maskz_cvtepi64_epi32(0, a);
4440        assert_eq_m128i(r, _mm_setzero_si128());
4441        let r = _mm256_maskz_cvtepi64_epi32(0b00001111, a);
4442        let e = _mm_set_epi32(1, 2, 3, 4);
4443        assert_eq_m128i(r, e);
4444    }
4445
4446    #[simd_test(enable = "avx512f,avx512vl")]
4447    unsafe fn test_mm_cvtepi64_epi32() {
4448        let a = _mm_set_epi64x(3, 4);
4449        let r = _mm_cvtepi64_epi32(a);
4450        let e = _mm_set_epi32(0, 0, 3, 4);
4451        assert_eq_m128i(r, e);
4452    }
4453
4454    #[simd_test(enable = "avx512f,avx512vl")]
4455    unsafe fn test_mm_mask_cvtepi64_epi32() {
4456        let a = _mm_set_epi64x(3, 4);
4457        let src = _mm_set1_epi32(0);
4458        let r = _mm_mask_cvtepi64_epi32(src, 0, a);
4459        assert_eq_m128i(r, src);
4460        let r = _mm_mask_cvtepi64_epi32(src, 0b00000011, a);
4461        let e = _mm_set_epi32(0, 0, 3, 4);
4462        assert_eq_m128i(r, e);
4463    }
4464
4465    #[simd_test(enable = "avx512f,avx512vl")]
4466    unsafe fn test_mm_maskz_cvtepi64_epi32() {
4467        let a = _mm_set_epi64x(3, 4);
4468        let r = _mm_maskz_cvtepi64_epi32(0, a);
4469        assert_eq_m128i(r, _mm_setzero_si128());
4470        let r = _mm_maskz_cvtepi64_epi32(0b00000011, a);
4471        let e = _mm_set_epi32(0, 0, 3, 4);
4472        assert_eq_m128i(r, e);
4473    }
4474
4475    #[simd_test(enable = "avx512f")]
4476    unsafe fn test_mm512_cvtepi64_epi16() {
4477        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4478        let r = _mm512_cvtepi64_epi16(a);
4479        let e = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4480        assert_eq_m128i(r, e);
4481    }
4482
4483    #[simd_test(enable = "avx512f")]
4484    unsafe fn test_mm512_mask_cvtepi64_epi16() {
4485        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4486        let src = _mm_set1_epi16(-1);
4487        let r = _mm512_mask_cvtepi64_epi16(src, 0, a);
4488        assert_eq_m128i(r, src);
4489        let r = _mm512_mask_cvtepi64_epi16(src, 0b00001111, a);
4490        let e = _mm_set_epi16(-1, -1, -1, -1, 12, 13, 14, 15);
4491        assert_eq_m128i(r, e);
4492    }
4493
4494    #[simd_test(enable = "avx512f")]
4495    unsafe fn test_mm512_maskz_cvtepi64_epi16() {
4496        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4497        let r = _mm512_maskz_cvtepi64_epi16(0, a);
4498        assert_eq_m128i(r, _mm_setzero_si128());
4499        let r = _mm512_maskz_cvtepi64_epi16(0b00001111, a);
4500        let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4501        assert_eq_m128i(r, e);
4502    }
4503
4504    #[simd_test(enable = "avx512f,avx512vl")]
4505    unsafe fn test_mm256_cvtepi64_epi16() {
4506        let a = _mm256_set_epi64x(12, 13, 14, 15);
4507        let r = _mm256_cvtepi64_epi16(a);
4508        let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4509        assert_eq_m128i(r, e);
4510    }
4511
4512    #[simd_test(enable = "avx512f,avx512vl")]
4513    unsafe fn test_mm256_mask_cvtepi64_epi16() {
4514        let a = _mm256_set_epi64x(12, 13, 14, 15);
4515        let src = _mm_set1_epi16(0);
4516        let r = _mm256_mask_cvtepi64_epi16(src, 0, a);
4517        assert_eq_m128i(r, src);
4518        let r = _mm256_mask_cvtepi64_epi16(src, 0b11111111, a);
4519        let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4520        assert_eq_m128i(r, e);
4521    }
4522
4523    #[simd_test(enable = "avx512f,avx512vl")]
4524    unsafe fn test_mm256_maskz_cvtepi64_epi16() {
4525        let a = _mm256_set_epi64x(12, 13, 14, 15);
4526        let r = _mm256_maskz_cvtepi64_epi16(0, a);
4527        assert_eq_m128i(r, _mm_setzero_si128());
4528        let r = _mm256_maskz_cvtepi64_epi16(0b11111111, a);
4529        let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4530        assert_eq_m128i(r, e);
4531    }
4532
4533    #[simd_test(enable = "avx512f,avx512vl")]
4534    unsafe fn test_mm_cvtepi64_epi16() {
4535        let a = _mm_set_epi64x(14, 15);
4536        let r = _mm_cvtepi64_epi16(a);
4537        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4538        assert_eq_m128i(r, e);
4539    }
4540
4541    #[simd_test(enable = "avx512f,avx512vl")]
4542    unsafe fn test_mm_mask_cvtepi64_epi16() {
4543        let a = _mm_set_epi64x(14, 15);
4544        let src = _mm_set1_epi16(0);
4545        let r = _mm_mask_cvtepi64_epi16(src, 0, a);
4546        assert_eq_m128i(r, src);
4547        let r = _mm_mask_cvtepi64_epi16(src, 0b11111111, a);
4548        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4549        assert_eq_m128i(r, e);
4550    }
4551
4552    #[simd_test(enable = "avx512f,avx512vl")]
4553    unsafe fn test_mm_maskz_cvtepi64_epi16() {
4554        let a = _mm_set_epi64x(14, 15);
4555        let r = _mm_maskz_cvtepi64_epi16(0, a);
4556        assert_eq_m128i(r, _mm_setzero_si128());
4557        let r = _mm_maskz_cvtepi64_epi16(0b11111111, a);
4558        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4559        assert_eq_m128i(r, e);
4560    }
4561
4562    #[simd_test(enable = "avx512f")]
4563    unsafe fn test_mm512_cvtepi64_epi8() {
4564        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4565        let r = _mm512_cvtepi64_epi8(a);
4566        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15);
4567        assert_eq_m128i(r, e);
4568    }
4569
4570    #[simd_test(enable = "avx512f")]
4571    unsafe fn test_mm512_mask_cvtepi64_epi8() {
4572        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4573        let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
4574        let r = _mm512_mask_cvtepi64_epi8(src, 0, a);
4575        assert_eq_m128i(r, src);
4576        let r = _mm512_mask_cvtepi64_epi8(src, 0b00001111, a);
4577        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, 12, 13, 14, 15);
4578        assert_eq_m128i(r, e);
4579    }
4580
4581    #[simd_test(enable = "avx512f")]
4582    unsafe fn test_mm512_maskz_cvtepi64_epi8() {
4583        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4584        let r = _mm512_maskz_cvtepi64_epi8(0, a);
4585        assert_eq_m128i(r, _mm_setzero_si128());
4586        let r = _mm512_maskz_cvtepi64_epi8(0b00001111, a);
4587        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4588        assert_eq_m128i(r, e);
4589    }
4590
4591    #[simd_test(enable = "avx512f,avx512vl")]
4592    unsafe fn test_mm256_cvtepi64_epi8() {
4593        let a = _mm256_set_epi64x(12, 13, 14, 15);
4594        let r = _mm256_cvtepi64_epi8(a);
4595        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4596        assert_eq_m128i(r, e);
4597    }
4598
4599    #[simd_test(enable = "avx512f,avx512vl")]
4600    unsafe fn test_mm256_mask_cvtepi64_epi8() {
4601        let a = _mm256_set_epi64x(12, 13, 14, 15);
4602        let src = _mm_set1_epi8(0);
4603        let r = _mm256_mask_cvtepi64_epi8(src, 0, a);
4604        assert_eq_m128i(r, src);
4605        let r = _mm256_mask_cvtepi64_epi8(src, 0b00001111, a);
4606        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4607        assert_eq_m128i(r, e);
4608    }
4609
4610    #[simd_test(enable = "avx512f,avx512vl")]
4611    unsafe fn test_mm256_maskz_cvtepi64_epi8() {
4612        let a = _mm256_set_epi64x(12, 13, 14, 15);
4613        let r = _mm256_maskz_cvtepi64_epi8(0, a);
4614        assert_eq_m128i(r, _mm_setzero_si128());
4615        let r = _mm256_maskz_cvtepi64_epi8(0b00001111, a);
4616        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4617        assert_eq_m128i(r, e);
4618    }
4619
4620    #[simd_test(enable = "avx512f,avx512vl")]
4621    unsafe fn test_mm_cvtepi64_epi8() {
4622        let a = _mm_set_epi64x(14, 15);
4623        let r = _mm_cvtepi64_epi8(a);
4624        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4625        assert_eq_m128i(r, e);
4626    }
4627
4628    #[simd_test(enable = "avx512f,avx512vl")]
4629    unsafe fn test_mm_mask_cvtepi64_epi8() {
4630        let a = _mm_set_epi64x(14, 15);
4631        let src = _mm_set1_epi8(0);
4632        let r = _mm_mask_cvtepi64_epi8(src, 0, a);
4633        assert_eq_m128i(r, src);
4634        let r = _mm_mask_cvtepi64_epi8(src, 0b00000011, a);
4635        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4636        assert_eq_m128i(r, e);
4637    }
4638
4639    #[simd_test(enable = "avx512f,avx512vl")]
4640    unsafe fn test_mm_maskz_cvtepi64_epi8() {
4641        let a = _mm_set_epi64x(14, 15);
4642        let r = _mm_maskz_cvtepi64_epi8(0, a);
4643        assert_eq_m128i(r, _mm_setzero_si128());
4644        let r = _mm_maskz_cvtepi64_epi8(0b00000011, a);
4645        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4646        assert_eq_m128i(r, e);
4647    }
4648
4649    #[simd_test(enable = "avx512f")]
4650    unsafe fn test_mm512_cvtsepi64_epi32() {
4651        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4652        let r = _mm512_cvtsepi64_epi32(a);
4653        let e = _mm256_set_epi32(0, 1, 2, 3, 4, 5, i32::MIN, i32::MAX);
4654        assert_eq_m256i(r, e);
4655    }
4656
4657    #[simd_test(enable = "avx512f")]
4658    unsafe fn test_mm512_mask_cvtsepi64_epi32() {
4659        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4660        let src = _mm256_set1_epi32(-1);
4661        let r = _mm512_mask_cvtsepi64_epi32(src, 0, a);
4662        assert_eq_m256i(r, src);
4663        let r = _mm512_mask_cvtsepi64_epi32(src, 0b00001111, a);
4664        let e = _mm256_set_epi32(-1, -1, -1, -1, 4, 5, i32::MIN, i32::MAX);
4665        assert_eq_m256i(r, e);
4666    }
4667
4668    #[simd_test(enable = "avx512f")]
4669    unsafe fn test_mm512_maskz_cvtsepi64_epi32() {
4670        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4671        let r = _mm512_maskz_cvtsepi64_epi32(0, a);
4672        assert_eq_m256i(r, _mm256_setzero_si256());
4673        let r = _mm512_maskz_cvtsepi64_epi32(0b00001111, a);
4674        let e = _mm256_set_epi32(0, 0, 0, 0, 4, 5, i32::MIN, i32::MAX);
4675        assert_eq_m256i(r, e);
4676    }
4677
4678    #[simd_test(enable = "avx512f,avx512vl")]
4679    unsafe fn test_mm256_cvtsepi64_epi32() {
4680        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4681        let r = _mm256_cvtsepi64_epi32(a);
4682        let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4683        assert_eq_m128i(r, e);
4684    }
4685
4686    #[simd_test(enable = "avx512f,avx512vl")]
4687    unsafe fn test_mm256_mask_cvtsepi64_epi32() {
4688        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4689        let src = _mm_set1_epi32(-1);
4690        let r = _mm256_mask_cvtsepi64_epi32(src, 0, a);
4691        assert_eq_m128i(r, src);
4692        let r = _mm256_mask_cvtsepi64_epi32(src, 0b00001111, a);
4693        let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4694        assert_eq_m128i(r, e);
4695    }
4696
4697    #[simd_test(enable = "avx512f,avx512vl")]
4698    unsafe fn test_mm256_maskz_cvtsepi64_epi32() {
4699        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4700        let r = _mm256_maskz_cvtsepi64_epi32(0, a);
4701        assert_eq_m128i(r, _mm_setzero_si128());
4702        let r = _mm256_maskz_cvtsepi64_epi32(0b00001111, a);
4703        let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4704        assert_eq_m128i(r, e);
4705    }
4706
4707    #[simd_test(enable = "avx512f,avx512vl")]
4708    unsafe fn test_mm_cvtsepi64_epi32() {
4709        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4710        let r = _mm_cvtsepi64_epi32(a);
4711        let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4712        assert_eq_m128i(r, e);
4713    }
4714
4715    #[simd_test(enable = "avx512f,avx512vl")]
4716    unsafe fn test_mm_mask_cvtsepi64_epi32() {
4717        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4718        let src = _mm_set1_epi32(0);
4719        let r = _mm_mask_cvtsepi64_epi32(src, 0, a);
4720        assert_eq_m128i(r, src);
4721        let r = _mm_mask_cvtsepi64_epi32(src, 0b00000011, a);
4722        let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4723        assert_eq_m128i(r, e);
4724    }
4725
4726    #[simd_test(enable = "avx512f,avx512vl")]
4727    unsafe fn test_mm_maskz_cvtsepi64_epi32() {
4728        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4729        let r = _mm_maskz_cvtsepi64_epi32(0, a);
4730        assert_eq_m128i(r, _mm_setzero_si128());
4731        let r = _mm_maskz_cvtsepi64_epi32(0b00000011, a);
4732        let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4733        assert_eq_m128i(r, e);
4734    }
4735
4736    #[simd_test(enable = "avx512f")]
4737    unsafe fn test_mm512_cvtsepi64_epi16() {
4738        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4739        let r = _mm512_cvtsepi64_epi16(a);
4740        let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, i16::MIN, i16::MAX);
4741        assert_eq_m128i(r, e);
4742    }
4743
4744    #[simd_test(enable = "avx512f")]
4745    unsafe fn test_mm512_mask_cvtsepi64_epi16() {
4746        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4747        let src = _mm_set1_epi16(-1);
4748        let r = _mm512_mask_cvtsepi64_epi16(src, 0, a);
4749        assert_eq_m128i(r, src);
4750        let r = _mm512_mask_cvtsepi64_epi16(src, 0b00001111, a);
4751        let e = _mm_set_epi16(-1, -1, -1, -1, 4, 5, i16::MIN, i16::MAX);
4752        assert_eq_m128i(r, e);
4753    }
4754
4755    #[simd_test(enable = "avx512f")]
4756    unsafe fn test_mm512_maskz_cvtsepi64_epi16() {
4757        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4758        let r = _mm512_maskz_cvtsepi64_epi16(0, a);
4759        assert_eq_m128i(r, _mm_setzero_si128());
4760        let r = _mm512_maskz_cvtsepi64_epi16(0b00001111, a);
4761        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4762        assert_eq_m128i(r, e);
4763    }
4764
4765    #[simd_test(enable = "avx512f,avx512vl")]
4766    unsafe fn test_mm256_cvtsepi64_epi16() {
4767        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4768        let r = _mm256_cvtsepi64_epi16(a);
4769        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4770        assert_eq_m128i(r, e);
4771    }
4772
4773    #[simd_test(enable = "avx512f,avx512vl")]
4774    unsafe fn test_mm256_mask_cvtsepi64_epi16() {
4775        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4776        let src = _mm_set1_epi16(0);
4777        let r = _mm256_mask_cvtsepi64_epi16(src, 0, a);
4778        assert_eq_m128i(r, src);
4779        let r = _mm256_mask_cvtsepi64_epi16(src, 0b00001111, a);
4780        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4781        assert_eq_m128i(r, e);
4782    }
4783
4784    #[simd_test(enable = "avx512f,avx512vl")]
4785    unsafe fn test_mm256_maskz_cvtsepi64_epi16() {
4786        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4787        let r = _mm256_maskz_cvtsepi64_epi16(0, a);
4788        assert_eq_m128i(r, _mm_setzero_si128());
4789        let r = _mm256_maskz_cvtsepi64_epi16(0b00001111, a);
4790        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4791        assert_eq_m128i(r, e);
4792    }
4793
4794    #[simd_test(enable = "avx512f,avx512vl")]
4795    unsafe fn test_mm_cvtsepi64_epi16() {
4796        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4797        let r = _mm_cvtsepi64_epi16(a);
4798        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4799        assert_eq_m128i(r, e);
4800    }
4801
4802    #[simd_test(enable = "avx512f,avx512vl")]
4803    unsafe fn test_mm_mask_cvtsepi64_epi16() {
4804        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4805        let src = _mm_set1_epi16(0);
4806        let r = _mm_mask_cvtsepi64_epi16(src, 0, a);
4807        assert_eq_m128i(r, src);
4808        let r = _mm_mask_cvtsepi64_epi16(src, 0b00000011, a);
4809        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4810        assert_eq_m128i(r, e);
4811    }
4812
4813    #[simd_test(enable = "avx512f,avx512vl")]
4814    unsafe fn test_mm_maskz_cvtsepi64_epi16() {
4815        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4816        let r = _mm_maskz_cvtsepi64_epi16(0, a);
4817        assert_eq_m128i(r, _mm_setzero_si128());
4818        let r = _mm_maskz_cvtsepi64_epi16(0b00000011, a);
4819        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4820        assert_eq_m128i(r, e);
4821    }
4822
4823    #[simd_test(enable = "avx512f")]
4824    unsafe fn test_mm512_cvtsepi64_epi8() {
4825        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4826        let r = _mm512_cvtsepi64_epi8(a);
4827        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, i8::MIN, i8::MAX);
4828        assert_eq_m128i(r, e);
4829    }
4830
4831    #[simd_test(enable = "avx512f")]
4832    unsafe fn test_mm512_mask_cvtsepi64_epi8() {
4833        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4834        let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
4835        let r = _mm512_mask_cvtsepi64_epi8(src, 0, a);
4836        assert_eq_m128i(r, src);
4837        let r = _mm512_mask_cvtsepi64_epi8(src, 0b00001111, a);
4838        #[rustfmt::skip]
4839        let e = _mm_set_epi8(
4840            0, 0, 0, 0,
4841            0, 0, 0, 0,
4842            -1, -1, -1, -1,
4843            4, 5, i8::MIN, i8::MAX,
4844        );
4845        assert_eq_m128i(r, e);
4846    }
4847
4848    #[simd_test(enable = "avx512f")]
4849    unsafe fn test_mm512_maskz_cvtsepi64_epi8() {
4850        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4851        let r = _mm512_maskz_cvtsepi64_epi8(0, a);
4852        assert_eq_m128i(r, _mm_setzero_si128());
4853        let r = _mm512_maskz_cvtsepi64_epi8(0b00001111, a);
4854        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4855        assert_eq_m128i(r, e);
4856    }
4857
4858    #[simd_test(enable = "avx512f,avx512vl")]
4859    unsafe fn test_mm256_cvtsepi64_epi8() {
4860        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4861        let r = _mm256_cvtsepi64_epi8(a);
4862        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4863        assert_eq_m128i(r, e);
4864    }
4865
4866    #[simd_test(enable = "avx512f,avx512vl")]
4867    unsafe fn test_mm256_mask_cvtsepi64_epi8() {
4868        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4869        let src = _mm_set1_epi8(0);
4870        let r = _mm256_mask_cvtsepi64_epi8(src, 0, a);
4871        assert_eq_m128i(r, src);
4872        let r = _mm256_mask_cvtsepi64_epi8(src, 0b00001111, a);
4873        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4874        assert_eq_m128i(r, e);
4875    }
4876
4877    #[simd_test(enable = "avx512f,avx512vl")]
4878    unsafe fn test_mm256_maskz_cvtsepi64_epi8() {
4879        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4880        let r = _mm256_maskz_cvtsepi64_epi8(0, a);
4881        assert_eq_m128i(r, _mm_setzero_si128());
4882        let r = _mm256_maskz_cvtsepi64_epi8(0b00001111, a);
4883        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4884        assert_eq_m128i(r, e);
4885    }
4886
4887    #[simd_test(enable = "avx512f,avx512vl")]
4888    unsafe fn test_mm_cvtsepi64_epi8() {
4889        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4890        let r = _mm_cvtsepi64_epi8(a);
4891        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4892        assert_eq_m128i(r, e);
4893    }
4894
4895    #[simd_test(enable = "avx512f,avx512vl")]
4896    unsafe fn test_mm_mask_cvtsepi64_epi8() {
4897        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4898        let src = _mm_set1_epi8(0);
4899        let r = _mm_mask_cvtsepi64_epi8(src, 0, a);
4900        assert_eq_m128i(r, src);
4901        let r = _mm_mask_cvtsepi64_epi8(src, 0b00000011, a);
4902        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4903        assert_eq_m128i(r, e);
4904    }
4905
4906    #[simd_test(enable = "avx512f,avx512vl")]
4907    unsafe fn test_mm_maskz_cvtsepi64_epi8() {
4908        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4909        let r = _mm_maskz_cvtsepi64_epi8(0, a);
4910        assert_eq_m128i(r, _mm_setzero_si128());
4911        let r = _mm_maskz_cvtsepi64_epi8(0b00000011, a);
4912        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4913        assert_eq_m128i(r, e);
4914    }
4915
4916    #[simd_test(enable = "avx512f")]
4917    unsafe fn test_mm512_cvtusepi64_epi32() {
4918        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4919        let r = _mm512_cvtusepi64_epi32(a);
4920        let e = _mm256_set_epi32(0, 1, 2, 3, 4, 5, -1, -1);
4921        assert_eq_m256i(r, e);
4922    }
4923
4924    #[simd_test(enable = "avx512f")]
4925    unsafe fn test_mm512_mask_cvtusepi64_epi32() {
4926        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4927        let src = _mm256_set1_epi32(-1);
4928        let r = _mm512_mask_cvtusepi64_epi32(src, 0, a);
4929        assert_eq_m256i(r, src);
4930        let r = _mm512_mask_cvtusepi64_epi32(src, 0b00001111, a);
4931        let e = _mm256_set_epi32(-1, -1, -1, -1, 4, 5, -1, -1);
4932        assert_eq_m256i(r, e);
4933    }
4934
4935    #[simd_test(enable = "avx512f")]
4936    unsafe fn test_mm512_maskz_cvtusepi64_epi32() {
4937        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4938        let r = _mm512_maskz_cvtusepi64_epi32(0, a);
4939        assert_eq_m256i(r, _mm256_setzero_si256());
4940        let r = _mm512_maskz_cvtusepi64_epi32(0b00001111, a);
4941        let e = _mm256_set_epi32(0, 0, 0, 0, 4, 5, -1, -1);
4942        assert_eq_m256i(r, e);
4943    }
4944
4945    #[simd_test(enable = "avx512f,avx512vl")]
4946    unsafe fn test_mm256_cvtusepi64_epi32() {
4947        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4948        let r = _mm256_cvtusepi64_epi32(a);
4949        let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4950        assert_eq_m128i(r, e);
4951    }
4952
4953    #[simd_test(enable = "avx512f,avx512vl")]
4954    unsafe fn test_mm256_mask_cvtusepi64_epi32() {
4955        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4956        let src = _mm_set1_epi32(0);
4957        let r = _mm256_mask_cvtusepi64_epi32(src, 0, a);
4958        assert_eq_m128i(r, src);
4959        let r = _mm256_mask_cvtusepi64_epi32(src, 0b00001111, a);
4960        let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4961        assert_eq_m128i(r, e);
4962    }
4963
4964    #[simd_test(enable = "avx512f,avx512vl")]
4965    unsafe fn test_mm256_maskz_cvtusepi64_epi32() {
4966        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4967        let r = _mm256_maskz_cvtusepi64_epi32(0, a);
4968        assert_eq_m128i(r, _mm_setzero_si128());
4969        let r = _mm256_maskz_cvtusepi64_epi32(0b00001111, a);
4970        let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4971        assert_eq_m128i(r, e);
4972    }
4973
4974    #[simd_test(enable = "avx512f,avx512vl")]
4975    unsafe fn test_mm_cvtusepi64_epi32() {
4976        let a = _mm_set_epi64x(6, i64::MAX);
4977        let r = _mm_cvtusepi64_epi32(a);
4978        let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
4979        assert_eq_m128i(r, e);
4980    }
4981
4982    #[simd_test(enable = "avx512f,avx512vl")]
4983    unsafe fn test_mm_mask_cvtusepi64_epi32() {
4984        let a = _mm_set_epi64x(6, i64::MAX);
4985        let src = _mm_set1_epi32(0);
4986        let r = _mm_mask_cvtusepi64_epi32(src, 0, a);
4987        assert_eq_m128i(r, src);
4988        let r = _mm_mask_cvtusepi64_epi32(src, 0b00000011, a);
4989        let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
4990        assert_eq_m128i(r, e);
4991    }
4992
4993    #[simd_test(enable = "avx512f,avx512vl")]
4994    unsafe fn test_mm_maskz_cvtusepi64_epi32() {
4995        let a = _mm_set_epi64x(6, i64::MAX);
4996        let r = _mm_maskz_cvtusepi64_epi32(0, a);
4997        assert_eq_m128i(r, _mm_setzero_si128());
4998        let r = _mm_maskz_cvtusepi64_epi32(0b00000011, a);
4999        let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
5000        assert_eq_m128i(r, e);
5001    }
5002
5003    #[simd_test(enable = "avx512f")]
5004    unsafe fn test_mm512_cvtusepi64_epi16() {
5005        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5006        let r = _mm512_cvtusepi64_epi16(a);
5007        let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, -1, -1);
5008        assert_eq_m128i(r, e);
5009    }
5010
5011    #[simd_test(enable = "avx512f")]
5012    unsafe fn test_mm512_mask_cvtusepi64_epi16() {
5013        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5014        let src = _mm_set1_epi16(-1);
5015        let r = _mm512_mask_cvtusepi64_epi16(src, 0, a);
5016        assert_eq_m128i(r, src);
5017        let r = _mm512_mask_cvtusepi64_epi16(src, 0b00001111, a);
5018        let e = _mm_set_epi16(-1, -1, -1, -1, 4, 5, -1, -1);
5019        assert_eq_m128i(r, e);
5020    }
5021
5022    #[simd_test(enable = "avx512f")]
5023    unsafe fn test_mm512_maskz_cvtusepi64_epi16() {
5024        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5025        let r = _mm512_maskz_cvtusepi64_epi16(0, a);
5026        assert_eq_m128i(r, _mm_setzero_si128());
5027        let r = _mm512_maskz_cvtusepi64_epi16(0b00001111, a);
5028        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, -1, -1);
5029        assert_eq_m128i(r, e);
5030    }
5031
5032    #[simd_test(enable = "avx512f,avx512vl")]
5033    unsafe fn test_mm256_cvtusepi64_epi16() {
5034        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5035        let r = _mm256_cvtusepi64_epi16(a);
5036        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
5037        assert_eq_m128i(r, e);
5038    }
5039
5040    #[simd_test(enable = "avx512f,avx512vl")]
5041    unsafe fn test_mm256_mask_cvtusepi64_epi16() {
5042        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5043        let src = _mm_set1_epi16(0);
5044        let r = _mm256_mask_cvtusepi64_epi16(src, 0, a);
5045        assert_eq_m128i(r, src);
5046        let r = _mm256_mask_cvtusepi64_epi16(src, 0b00001111, a);
5047        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
5048        assert_eq_m128i(r, e);
5049    }
5050
5051    #[simd_test(enable = "avx512f,avx512vl")]
5052    unsafe fn test_mm256_maskz_cvtusepi64_epi16() {
5053        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5054        let r = _mm256_maskz_cvtusepi64_epi16(0, a);
5055        assert_eq_m128i(r, _mm_setzero_si128());
5056        let r = _mm256_maskz_cvtusepi64_epi16(0b00001111, a);
5057        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
5058        assert_eq_m128i(r, e);
5059    }
5060
5061    #[simd_test(enable = "avx512f,avx512vl")]
5062    unsafe fn test_mm_cvtusepi64_epi16() {
5063        let a = _mm_set_epi64x(6, i64::MAX);
5064        let r = _mm_cvtusepi64_epi16(a);
5065        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
5066        assert_eq_m128i(r, e);
5067    }
5068
5069    #[simd_test(enable = "avx512f,avx512vl")]
5070    unsafe fn test_mm_mask_cvtusepi64_epi16() {
5071        let a = _mm_set_epi64x(6, i64::MAX);
5072        let src = _mm_set1_epi16(0);
5073        let r = _mm_mask_cvtusepi64_epi16(src, 0, a);
5074        assert_eq_m128i(r, src);
5075        let r = _mm_mask_cvtusepi64_epi16(src, 0b00000011, a);
5076        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
5077        assert_eq_m128i(r, e);
5078    }
5079
5080    #[simd_test(enable = "avx512f,avx512vl")]
5081    unsafe fn test_mm_maskz_cvtusepi64_epi16() {
5082        let a = _mm_set_epi64x(6, i64::MAX);
5083        let r = _mm_maskz_cvtusepi64_epi16(0, a);
5084        assert_eq_m128i(r, _mm_setzero_si128());
5085        let r = _mm_maskz_cvtusepi64_epi16(0b00000011, a);
5086        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
5087        assert_eq_m128i(r, e);
5088    }
5089
5090    #[simd_test(enable = "avx512f")]
5091    unsafe fn test_mm512_cvtusepi64_epi8() {
5092        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5093        let r = _mm512_cvtusepi64_epi8(a);
5094        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, -1, -1);
5095        assert_eq_m128i(r, e);
5096    }
5097
5098    #[simd_test(enable = "avx512f")]
5099    unsafe fn test_mm512_mask_cvtusepi64_epi8() {
5100        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5101        let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
5102        let r = _mm512_mask_cvtusepi64_epi8(src, 0, a);
5103        assert_eq_m128i(r, src);
5104        let r = _mm512_mask_cvtusepi64_epi8(src, 0b00001111, a);
5105        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, 4, 5, -1, -1);
5106        assert_eq_m128i(r, e);
5107    }
5108
5109    #[simd_test(enable = "avx512f")]
5110    unsafe fn test_mm512_maskz_cvtusepi64_epi8() {
5111        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5112        let r = _mm512_maskz_cvtusepi64_epi8(0, a);
5113        assert_eq_m128i(r, _mm_setzero_si128());
5114        let r = _mm512_maskz_cvtusepi64_epi8(0b00001111, a);
5115        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, -1, -1);
5116        assert_eq_m128i(r, e);
5117    }
5118
5119    #[simd_test(enable = "avx512f,avx512vl")]
5120    unsafe fn test_mm256_cvtusepi64_epi8() {
5121        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5122        let r = _mm256_cvtusepi64_epi8(a);
5123        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
5124        assert_eq_m128i(r, e);
5125    }
5126
5127    #[simd_test(enable = "avx512f,avx512vl")]
5128    unsafe fn test_mm256_mask_cvtusepi64_epi8() {
5129        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5130        let src = _mm_set1_epi8(0);
5131        let r = _mm256_mask_cvtusepi64_epi8(src, 0, a);
5132        assert_eq_m128i(r, src);
5133        let r = _mm256_mask_cvtusepi64_epi8(src, 0b00001111, a);
5134        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
5135        assert_eq_m128i(r, e);
5136    }
5137
5138    #[simd_test(enable = "avx512f,avx512vl")]
5139    unsafe fn test_mm256_maskz_cvtusepi64_epi8() {
5140        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5141        let r = _mm256_maskz_cvtusepi64_epi8(0, a);
5142        assert_eq_m128i(r, _mm_setzero_si128());
5143        let r = _mm256_maskz_cvtusepi64_epi8(0b00001111, a);
5144        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
5145        assert_eq_m128i(r, e);
5146    }
5147
5148    #[simd_test(enable = "avx512f,avx512vl")]
5149    unsafe fn test_mm_cvtusepi64_epi8() {
5150        let a = _mm_set_epi64x(6, i64::MAX);
5151        let r = _mm_cvtusepi64_epi8(a);
5152        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
5153        assert_eq_m128i(r, e);
5154    }
5155
5156    #[simd_test(enable = "avx512f,avx512vl")]
5157    unsafe fn test_mm_mask_cvtusepi64_epi8() {
5158        let a = _mm_set_epi64x(6, i64::MAX);
5159        let src = _mm_set1_epi8(0);
5160        let r = _mm_mask_cvtusepi64_epi8(src, 0, a);
5161        assert_eq_m128i(r, src);
5162        let r = _mm_mask_cvtusepi64_epi8(src, 0b00000011, a);
5163        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
5164        assert_eq_m128i(r, e);
5165    }
5166
5167    #[simd_test(enable = "avx512f,avx512vl")]
5168    unsafe fn test_mm_maskz_cvtusepi64_epi8() {
5169        let a = _mm_set_epi64x(6, i64::MAX);
5170        let r = _mm_maskz_cvtusepi64_epi8(0, a);
5171        assert_eq_m128i(r, _mm_setzero_si128());
5172        let r = _mm_maskz_cvtusepi64_epi8(0b00000011, a);
5173        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
5174        assert_eq_m128i(r, e);
5175    }
5176
5177    #[simd_test(enable = "avx512f")]
5178    unsafe fn test_mm512_cvtt_roundpd_epi32() {
5179        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5180        let r = _mm512_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(a);
5181        let e = _mm256_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7);
5182        assert_eq_m256i(r, e);
5183    }
5184
5185    #[simd_test(enable = "avx512f")]
5186    unsafe fn test_mm512_mask_cvtt_roundpd_epi32() {
5187        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5188        let src = _mm256_set1_epi32(0);
5189        let r = _mm512_mask_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(src, 0, a);
5190        assert_eq_m256i(r, src);
5191        let r = _mm512_mask_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(src, 0b00001111, a);
5192        let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5193        assert_eq_m256i(r, e);
5194    }
5195
5196    #[simd_test(enable = "avx512f")]
5197    unsafe fn test_mm512_maskz_cvtt_roundpd_epi32() {
5198        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5199        let r = _mm512_maskz_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(0, a);
5200        assert_eq_m256i(r, _mm256_setzero_si256());
5201        let r = _mm512_maskz_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(0b00001111, a);
5202        let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5203        assert_eq_m256i(r, e);
5204    }
5205
5206    #[simd_test(enable = "avx512f")]
5207    unsafe fn test_mm512_cvtt_roundpd_epu32() {
5208        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5209        let r = _mm512_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(a);
5210        let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
5211        assert_eq_m256i(r, e);
5212    }
5213
5214    #[simd_test(enable = "avx512f")]
5215    unsafe fn test_mm512_mask_cvtt_roundpd_epu32() {
5216        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5217        let src = _mm256_set1_epi32(0);
5218        let r = _mm512_mask_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(src, 0, a);
5219        assert_eq_m256i(r, src);
5220        let r = _mm512_mask_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(src, 0b00001111, a);
5221        let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5222        assert_eq_m256i(r, e);
5223    }
5224
5225    #[simd_test(enable = "avx512f")]
5226    unsafe fn test_mm512_maskz_cvtt_roundpd_epu32() {
5227        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5228        let r = _mm512_maskz_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(0, a);
5229        assert_eq_m256i(r, _mm256_setzero_si256());
5230        let r = _mm512_maskz_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(0b00001111, a);
5231        let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5232        assert_eq_m256i(r, e);
5233    }
5234
5235    #[simd_test(enable = "avx512f")]
5236    unsafe fn test_mm512_cvttpd_epi32() {
5237        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5238        let r = _mm512_cvttpd_epi32(a);
5239        let e = _mm256_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7);
5240        assert_eq_m256i(r, e);
5241    }
5242
5243    #[simd_test(enable = "avx512f")]
5244    unsafe fn test_mm512_mask_cvttpd_epi32() {
5245        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5246        let src = _mm256_set1_epi32(0);
5247        let r = _mm512_mask_cvttpd_epi32(src, 0, a);
5248        assert_eq_m256i(r, src);
5249        let r = _mm512_mask_cvttpd_epi32(src, 0b00001111, a);
5250        let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5251        assert_eq_m256i(r, e);
5252    }
5253
5254    #[simd_test(enable = "avx512f")]
5255    unsafe fn test_mm512_maskz_cvttpd_epi32() {
5256        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5257        let r = _mm512_maskz_cvttpd_epi32(0, a);
5258        assert_eq_m256i(r, _mm256_setzero_si256());
5259        let r = _mm512_maskz_cvttpd_epi32(0b00001111, a);
5260        let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5261        assert_eq_m256i(r, e);
5262    }
5263
5264    #[simd_test(enable = "avx512f,avx512vl")]
5265    unsafe fn test_mm256_mask_cvttpd_epi32() {
5266        let a = _mm256_setr_pd(4., -5.5, 6., -7.5);
5267        let src = _mm_set1_epi32(0);
5268        let r = _mm256_mask_cvttpd_epi32(src, 0, a);
5269        assert_eq_m128i(r, src);
5270        let r = _mm256_mask_cvttpd_epi32(src, 0b00001111, a);
5271        let e = _mm_setr_epi32(4, -5, 6, -7);
5272        assert_eq_m128i(r, e);
5273    }
5274
5275    #[simd_test(enable = "avx512f,avx512vl")]
5276    unsafe fn test_mm256_maskz_cvttpd_epi32() {
5277        let a = _mm256_setr_pd(4., -5.5, 6., -7.5);
5278        let r = _mm256_maskz_cvttpd_epi32(0, a);
5279        assert_eq_m128i(r, _mm_setzero_si128());
5280        let r = _mm256_maskz_cvttpd_epi32(0b00001111, a);
5281        let e = _mm_setr_epi32(4, -5, 6, -7);
5282        assert_eq_m128i(r, e);
5283    }
5284
5285    #[simd_test(enable = "avx512f,avx512vl")]
5286    unsafe fn test_mm_mask_cvttpd_epi32() {
5287        let a = _mm_set_pd(6., -7.5);
5288        let src = _mm_set1_epi32(0);
5289        let r = _mm_mask_cvttpd_epi32(src, 0, a);
5290        assert_eq_m128i(r, src);
5291        let r = _mm_mask_cvttpd_epi32(src, 0b00000011, a);
5292        let e = _mm_set_epi32(0, 0, 6, -7);
5293        assert_eq_m128i(r, e);
5294    }
5295
5296    #[simd_test(enable = "avx512f,avx512vl")]
5297    unsafe fn test_mm_maskz_cvttpd_epi32() {
5298        let a = _mm_set_pd(6., -7.5);
5299        let r = _mm_maskz_cvttpd_epi32(0, a);
5300        assert_eq_m128i(r, _mm_setzero_si128());
5301        let r = _mm_maskz_cvttpd_epi32(0b00000011, a);
5302        let e = _mm_set_epi32(0, 0, 6, -7);
5303        assert_eq_m128i(r, e);
5304    }
5305
5306    #[simd_test(enable = "avx512f")]
5307    unsafe fn test_mm512_cvttpd_epu32() {
5308        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5309        let r = _mm512_cvttpd_epu32(a);
5310        let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
5311        assert_eq_m256i(r, e);
5312    }
5313
5314    #[simd_test(enable = "avx512f")]
5315    unsafe fn test_mm512_mask_cvttpd_epu32() {
5316        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5317        let src = _mm256_set1_epi32(0);
5318        let r = _mm512_mask_cvttpd_epu32(src, 0, a);
5319        assert_eq_m256i(r, src);
5320        let r = _mm512_mask_cvttpd_epu32(src, 0b00001111, a);
5321        let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5322        assert_eq_m256i(r, e);
5323    }
5324
5325    #[simd_test(enable = "avx512f")]
5326    unsafe fn test_mm512_maskz_cvttpd_epu32() {
5327        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5328        let r = _mm512_maskz_cvttpd_epu32(0, a);
5329        assert_eq_m256i(r, _mm256_setzero_si256());
5330        let r = _mm512_maskz_cvttpd_epu32(0b00001111, a);
5331        let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5332        assert_eq_m256i(r, e);
5333    }
5334
5335    #[simd_test(enable = "avx512f,avx512vl")]
5336    unsafe fn test_mm256_cvttpd_epu32() {
5337        let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5338        let r = _mm256_cvttpd_epu32(a);
5339        let e = _mm_set_epi32(4, 5, 6, 7);
5340        assert_eq_m128i(r, e);
5341    }
5342
5343    #[simd_test(enable = "avx512f,avx512vl")]
5344    unsafe fn test_mm256_mask_cvttpd_epu32() {
5345        let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5346        let src = _mm_set1_epi32(0);
5347        let r = _mm256_mask_cvttpd_epu32(src, 0, a);
5348        assert_eq_m128i(r, src);
5349        let r = _mm256_mask_cvttpd_epu32(src, 0b00001111, a);
5350        let e = _mm_set_epi32(4, 5, 6, 7);
5351        assert_eq_m128i(r, e);
5352    }
5353
5354    #[simd_test(enable = "avx512f,avx512vl")]
5355    unsafe fn test_mm256_maskz_cvttpd_epu32() {
5356        let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5357        let r = _mm256_maskz_cvttpd_epu32(0, a);
5358        assert_eq_m128i(r, _mm_setzero_si128());
5359        let r = _mm256_maskz_cvttpd_epu32(0b00001111, a);
5360        let e = _mm_set_epi32(4, 5, 6, 7);
5361        assert_eq_m128i(r, e);
5362    }
5363
5364    #[simd_test(enable = "avx512f,avx512vl")]
5365    unsafe fn test_mm_cvttpd_epu32() {
5366        let a = _mm_set_pd(6., 7.5);
5367        let r = _mm_cvttpd_epu32(a);
5368        let e = _mm_set_epi32(0, 0, 6, 7);
5369        assert_eq_m128i(r, e);
5370    }
5371
5372    #[simd_test(enable = "avx512f,avx512vl")]
5373    unsafe fn test_mm_mask_cvttpd_epu32() {
5374        let a = _mm_set_pd(6., 7.5);
5375        let src = _mm_set1_epi32(0);
5376        let r = _mm_mask_cvttpd_epu32(src, 0, a);
5377        assert_eq_m128i(r, src);
5378        let r = _mm_mask_cvttpd_epu32(src, 0b00000011, a);
5379        let e = _mm_set_epi32(0, 0, 6, 7);
5380        assert_eq_m128i(r, e);
5381    }
5382
5383    #[simd_test(enable = "avx512f,avx512vl")]
5384    unsafe fn test_mm_maskz_cvttpd_epu32() {
5385        let a = _mm_set_pd(6., 7.5);
5386        let r = _mm_maskz_cvttpd_epu32(0, a);
5387        assert_eq_m128i(r, _mm_setzero_si128());
5388        let r = _mm_maskz_cvttpd_epu32(0b00000011, a);
5389        let e = _mm_set_epi32(0, 0, 6, 7);
5390        assert_eq_m128i(r, e);
5391    }
5392
5393    #[simd_test(enable = "avx512f")]
5394    unsafe fn test_mm512_add_round_pd() {
5395        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5396        let b = _mm512_set1_pd(-1.);
5397        let r = _mm512_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5398        let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -1.0);
5399        assert_eq_m512d(r, e);
5400        let r = _mm512_add_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5401        let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -0.9999999999999999);
5402        assert_eq_m512d(r, e);
5403    }
5404
5405    #[simd_test(enable = "avx512f")]
5406    unsafe fn test_mm512_mask_add_round_pd() {
5407        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5408        let b = _mm512_set1_pd(-1.);
5409        let r = _mm512_mask_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5410            a, 0, a, b,
5411        );
5412        assert_eq_m512d(r, a);
5413        let r = _mm512_mask_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5414            a, 0b11110000, a, b,
5415        );
5416        let e = _mm512_setr_pd(8., 9.5, 10., 11.5, 11., 12.5, 13., -1.0);
5417        assert_eq_m512d(r, e);
5418    }
5419
5420    #[simd_test(enable = "avx512f")]
5421    unsafe fn test_mm512_maskz_add_round_pd() {
5422        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5423        let b = _mm512_set1_pd(-1.);
5424        let r =
5425            _mm512_maskz_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5426        assert_eq_m512d(r, _mm512_setzero_pd());
5427        let r = _mm512_maskz_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5428            0b11110000, a, b,
5429        );
5430        let e = _mm512_setr_pd(0., 0., 0., 0., 11., 12.5, 13., -1.0);
5431        assert_eq_m512d(r, e);
5432    }
5433
5434    #[simd_test(enable = "avx512f")]
5435    unsafe fn test_mm512_sub_round_pd() {
5436        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5437        let b = _mm512_set1_pd(1.);
5438        let r = _mm512_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5439        let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -1.0);
5440        assert_eq_m512d(r, e);
5441        let r = _mm512_sub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5442        let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -0.9999999999999999);
5443        assert_eq_m512d(r, e);
5444    }
5445
5446    #[simd_test(enable = "avx512f")]
5447    unsafe fn test_mm512_mask_sub_round_pd() {
5448        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5449        let b = _mm512_set1_pd(1.);
5450        let r = _mm512_mask_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5451            a, 0, a, b,
5452        );
5453        assert_eq_m512d(r, a);
5454        let r = _mm512_mask_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5455            a, 0b11110000, a, b,
5456        );
5457        let e = _mm512_setr_pd(8., 9.5, 10., 11.5, 11., 12.5, 13., -1.0);
5458        assert_eq_m512d(r, e);
5459    }
5460
5461    #[simd_test(enable = "avx512f")]
5462    unsafe fn test_mm512_maskz_sub_round_pd() {
5463        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5464        let b = _mm512_set1_pd(1.);
5465        let r =
5466            _mm512_maskz_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5467        assert_eq_m512d(r, _mm512_setzero_pd());
5468        let r = _mm512_maskz_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5469            0b11110000, a, b,
5470        );
5471        let e = _mm512_setr_pd(0., 0., 0., 0., 11., 12.5, 13., -1.0);
5472        assert_eq_m512d(r, e);
5473    }
5474
5475    #[simd_test(enable = "avx512f")]
5476    unsafe fn test_mm512_mul_round_pd() {
5477        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5478        let b = _mm512_set1_pd(0.1);
5479        let r = _mm512_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5480        let e = _mm512_setr_pd(
5481            0.8,
5482            0.9500000000000001,
5483            1.,
5484            1.1500000000000001,
5485            1.2000000000000002,
5486            1.35,
5487            1.4000000000000001,
5488            0.,
5489        );
5490        assert_eq_m512d(r, e);
5491        let r = _mm512_mul_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5492        let e = _mm512_setr_pd(0.8, 0.95, 1.0, 1.15, 1.2, 1.3499999999999999, 1.4, 0.0);
5493        assert_eq_m512d(r, e);
5494    }
5495
5496    #[simd_test(enable = "avx512f")]
5497    unsafe fn test_mm512_mask_mul_round_pd() {
5498        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5499        let b = _mm512_set1_pd(0.1);
5500        let r = _mm512_mask_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5501            a, 0, a, b,
5502        );
5503        assert_eq_m512d(r, a);
5504        let r = _mm512_mask_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5505            a, 0b11110000, a, b,
5506        );
5507        let e = _mm512_setr_pd(
5508            8.,
5509            9.5,
5510            10.,
5511            11.5,
5512            1.2000000000000002,
5513            1.35,
5514            1.4000000000000001,
5515            0.,
5516        );
5517        assert_eq_m512d(r, e);
5518    }
5519
5520    #[simd_test(enable = "avx512f")]
5521    unsafe fn test_mm512_maskz_mul_round_pd() {
5522        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5523        let b = _mm512_set1_pd(0.1);
5524        let r =
5525            _mm512_maskz_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5526        assert_eq_m512d(r, _mm512_setzero_pd());
5527        let r = _mm512_maskz_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5528            0b11110000, a, b,
5529        );
5530        let e = _mm512_setr_pd(
5531            0.,
5532            0.,
5533            0.,
5534            0.,
5535            1.2000000000000002,
5536            1.35,
5537            1.4000000000000001,
5538            0.,
5539        );
5540        assert_eq_m512d(r, e);
5541    }
5542
5543    #[simd_test(enable = "avx512f")]
5544    unsafe fn test_mm512_div_round_pd() {
5545        let a = _mm512_set1_pd(1.);
5546        let b = _mm512_set1_pd(3.);
5547        let r = _mm512_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5548        let e = _mm512_set1_pd(0.3333333333333333);
5549        assert_eq_m512d(r, e);
5550        let r = _mm512_div_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5551        let e = _mm512_set1_pd(0.3333333333333333);
5552        assert_eq_m512d(r, e);
5553    }
5554
5555    #[simd_test(enable = "avx512f")]
5556    unsafe fn test_mm512_mask_div_round_pd() {
5557        let a = _mm512_set1_pd(1.);
5558        let b = _mm512_set1_pd(3.);
5559        let r = _mm512_mask_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5560            a, 0, a, b,
5561        );
5562        assert_eq_m512d(r, a);
5563        let r = _mm512_mask_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5564            a, 0b11110000, a, b,
5565        );
5566        let e = _mm512_setr_pd(
5567            1.,
5568            1.,
5569            1.,
5570            1.,
5571            0.3333333333333333,
5572            0.3333333333333333,
5573            0.3333333333333333,
5574            0.3333333333333333,
5575        );
5576        assert_eq_m512d(r, e);
5577    }
5578
5579    #[simd_test(enable = "avx512f")]
5580    unsafe fn test_mm512_maskz_div_round_pd() {
5581        let a = _mm512_set1_pd(1.);
5582        let b = _mm512_set1_pd(3.);
5583        let r =
5584            _mm512_maskz_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5585        assert_eq_m512d(r, _mm512_setzero_pd());
5586        let r = _mm512_maskz_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5587            0b11110000, a, b,
5588        );
5589        let e = _mm512_setr_pd(
5590            0.,
5591            0.,
5592            0.,
5593            0.,
5594            0.3333333333333333,
5595            0.3333333333333333,
5596            0.3333333333333333,
5597            0.3333333333333333,
5598        );
5599        assert_eq_m512d(r, e);
5600    }
5601
5602    #[simd_test(enable = "avx512f")]
5603    unsafe fn test_mm512_sqrt_round_pd() {
5604        let a = _mm512_set1_pd(3.);
5605        let r = _mm512_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
5606        let e = _mm512_set1_pd(1.7320508075688772);
5607        assert_eq_m512d(r, e);
5608        let r = _mm512_sqrt_round_pd::<{ _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC }>(a);
5609        let e = _mm512_set1_pd(1.7320508075688774);
5610        assert_eq_m512d(r, e);
5611    }
5612
5613    #[simd_test(enable = "avx512f")]
5614    unsafe fn test_mm512_mask_sqrt_round_pd() {
5615        let a = _mm512_set1_pd(3.);
5616        let r =
5617            _mm512_mask_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, 0, a);
5618        assert_eq_m512d(r, a);
5619        let r = _mm512_mask_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5620            a, 0b11110000, a,
5621        );
5622        let e = _mm512_setr_pd(
5623            3.,
5624            3.,
5625            3.,
5626            3.,
5627            1.7320508075688772,
5628            1.7320508075688772,
5629            1.7320508075688772,
5630            1.7320508075688772,
5631        );
5632        assert_eq_m512d(r, e);
5633    }
5634
5635    #[simd_test(enable = "avx512f")]
5636    unsafe fn test_mm512_maskz_sqrt_round_pd() {
5637        let a = _mm512_set1_pd(3.);
5638        let r =
5639            _mm512_maskz_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a);
5640        assert_eq_m512d(r, _mm512_setzero_pd());
5641        let r = _mm512_maskz_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5642            0b11110000, a,
5643        );
5644        let e = _mm512_setr_pd(
5645            0.,
5646            0.,
5647            0.,
5648            0.,
5649            1.7320508075688772,
5650            1.7320508075688772,
5651            1.7320508075688772,
5652            1.7320508075688772,
5653        );
5654        assert_eq_m512d(r, e);
5655    }
5656
5657    #[simd_test(enable = "avx512f")]
5658    unsafe fn test_mm512_fmadd_round_pd() {
5659        let a = _mm512_set1_pd(0.000000000000000007);
5660        let b = _mm512_set1_pd(1.);
5661        let c = _mm512_set1_pd(-1.);
5662        let r = _mm512_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5663        let e = _mm512_set1_pd(-1.);
5664        assert_eq_m512d(r, e);
5665        let r = _mm512_fmadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5666        let e = _mm512_set1_pd(-0.9999999999999999);
5667        assert_eq_m512d(r, e);
5668    }
5669
5670    #[simd_test(enable = "avx512f")]
5671    unsafe fn test_mm512_mask_fmadd_round_pd() {
5672        let a = _mm512_set1_pd(0.000000000000000007);
5673        let b = _mm512_set1_pd(1.);
5674        let c = _mm512_set1_pd(-1.);
5675        let r = _mm512_mask_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5676            a, 0, b, c,
5677        );
5678        assert_eq_m512d(r, a);
5679        let r = _mm512_mask_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5680            a, 0b00001111, b, c,
5681        );
5682        let e = _mm512_setr_pd(
5683            -1.,
5684            -1.,
5685            -1.,
5686            -1.,
5687            0.000000000000000007,
5688            0.000000000000000007,
5689            0.000000000000000007,
5690            0.000000000000000007,
5691        );
5692        assert_eq_m512d(r, e);
5693    }
5694
5695    #[simd_test(enable = "avx512f")]
5696    unsafe fn test_mm512_maskz_fmadd_round_pd() {
5697        let a = _mm512_set1_pd(0.000000000000000007);
5698        let b = _mm512_set1_pd(1.);
5699        let c = _mm512_set1_pd(-1.);
5700        let r = _mm512_maskz_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5701            0, a, b, c,
5702        );
5703        assert_eq_m512d(r, _mm512_setzero_pd());
5704        let r = _mm512_maskz_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5705            0b00001111, a, b, c,
5706        );
5707        let e = _mm512_setr_pd(-1., -1., -1., -1., 0., 0., 0., 0.);
5708        assert_eq_m512d(r, e);
5709    }
5710
5711    #[simd_test(enable = "avx512f")]
5712    unsafe fn test_mm512_mask3_fmadd_round_pd() {
5713        let a = _mm512_set1_pd(0.000000000000000007);
5714        let b = _mm512_set1_pd(1.);
5715        let c = _mm512_set1_pd(-1.);
5716        let r = _mm512_mask3_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5717            a, b, c, 0,
5718        );
5719        assert_eq_m512d(r, c);
5720        let r = _mm512_mask3_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5721            a, b, c, 0b00001111,
5722        );
5723        let e = _mm512_setr_pd(-1., -1., -1., -1., -1., -1., -1., -1.);
5724        assert_eq_m512d(r, e);
5725    }
5726
5727    #[simd_test(enable = "avx512f")]
5728    unsafe fn test_mm512_fmsub_round_pd() {
5729        let a = _mm512_set1_pd(0.000000000000000007);
5730        let b = _mm512_set1_pd(1.);
5731        let c = _mm512_set1_pd(1.);
5732        let r = _mm512_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5733        let e = _mm512_set1_pd(-1.);
5734        assert_eq_m512d(r, e);
5735        let r = _mm512_fmsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5736        let e = _mm512_set1_pd(-0.9999999999999999);
5737        assert_eq_m512d(r, e);
5738    }
5739
5740    #[simd_test(enable = "avx512f")]
5741    unsafe fn test_mm512_mask_fmsub_round_pd() {
5742        let a = _mm512_set1_pd(0.000000000000000007);
5743        let b = _mm512_set1_pd(1.);
5744        let c = _mm512_set1_pd(1.);
5745        let r = _mm512_mask_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5746            a, 0, b, c,
5747        );
5748        assert_eq_m512d(r, a);
5749        let r = _mm512_mask_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5750            a, 0b00001111, b, c,
5751        );
5752        let e = _mm512_setr_pd(
5753            -1.,
5754            -1.,
5755            -1.,
5756            -1.,
5757            0.000000000000000007,
5758            0.000000000000000007,
5759            0.000000000000000007,
5760            0.000000000000000007,
5761        );
5762        assert_eq_m512d(r, e);
5763    }
5764
5765    #[simd_test(enable = "avx512f")]
5766    unsafe fn test_mm512_maskz_fmsub_round_pd() {
5767        let a = _mm512_set1_pd(0.000000000000000007);
5768        let b = _mm512_set1_pd(1.);
5769        let c = _mm512_set1_pd(1.);
5770        let r = _mm512_maskz_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5771            0, a, b, c,
5772        );
5773        assert_eq_m512d(r, _mm512_setzero_pd());
5774        let r = _mm512_maskz_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5775            0b00001111, a, b, c,
5776        );
5777        let e = _mm512_setr_pd(-1., -1., -1., -1., 0., 0., 0., 0.);
5778        assert_eq_m512d(r, e);
5779    }
5780
5781    #[simd_test(enable = "avx512f")]
5782    unsafe fn test_mm512_mask3_fmsub_round_pd() {
5783        let a = _mm512_set1_pd(0.000000000000000007);
5784        let b = _mm512_set1_pd(1.);
5785        let c = _mm512_set1_pd(1.);
5786        let r = _mm512_mask3_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5787            a, b, c, 0,
5788        );
5789        assert_eq_m512d(r, c);
5790        let r = _mm512_mask3_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5791            a, b, c, 0b00001111,
5792        );
5793        let e = _mm512_setr_pd(-1., -1., -1., -1., 1., 1., 1., 1.);
5794        assert_eq_m512d(r, e);
5795    }
5796
5797    #[simd_test(enable = "avx512f")]
5798    unsafe fn test_mm512_fmaddsub_round_pd() {
5799        let a = _mm512_set1_pd(0.000000000000000007);
5800        let b = _mm512_set1_pd(1.);
5801        let c = _mm512_set1_pd(-1.);
5802        let r =
5803            _mm512_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5804        let e = _mm512_setr_pd(1., -1., 1., -1., 1., -1., 1., -1.);
5805        assert_eq_m512d(r, e);
5806        let r = _mm512_fmaddsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5807        let e = _mm512_setr_pd(
5808            1.,
5809            -0.9999999999999999,
5810            1.,
5811            -0.9999999999999999,
5812            1.,
5813            -0.9999999999999999,
5814            1.,
5815            -0.9999999999999999,
5816        );
5817        assert_eq_m512d(r, e);
5818    }
5819
5820    #[simd_test(enable = "avx512f")]
5821    unsafe fn test_mm512_mask_fmaddsub_round_pd() {
5822        let a = _mm512_set1_pd(0.000000000000000007);
5823        let b = _mm512_set1_pd(1.);
5824        let c = _mm512_set1_pd(-1.);
5825        let r = _mm512_mask_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5826            a, 0, b, c,
5827        );
5828        assert_eq_m512d(r, a);
5829        let r = _mm512_mask_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5830            a, 0b00001111, b, c,
5831        );
5832        let e = _mm512_setr_pd(
5833            1.,
5834            -1.,
5835            1.,
5836            -1.,
5837            0.000000000000000007,
5838            0.000000000000000007,
5839            0.000000000000000007,
5840            0.000000000000000007,
5841        );
5842        assert_eq_m512d(r, e);
5843    }
5844
5845    #[simd_test(enable = "avx512f")]
5846    unsafe fn test_mm512_maskz_fmaddsub_round_pd() {
5847        let a = _mm512_set1_pd(0.000000000000000007);
5848        let b = _mm512_set1_pd(1.);
5849        let c = _mm512_set1_pd(-1.);
5850        let r = _mm512_maskz_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5851            0, a, b, c,
5852        );
5853        assert_eq_m512d(r, _mm512_setzero_pd());
5854        let r = _mm512_maskz_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5855            0b00001111, a, b, c,
5856        );
5857        let e = _mm512_setr_pd(1., -1., 1., -1., 0., 0., 0., 0.);
5858        assert_eq_m512d(r, e);
5859    }
5860
5861    #[simd_test(enable = "avx512f")]
5862    unsafe fn test_mm512_mask3_fmaddsub_round_pd() {
5863        let a = _mm512_set1_pd(0.000000000000000007);
5864        let b = _mm512_set1_pd(1.);
5865        let c = _mm512_set1_pd(-1.);
5866        let r = _mm512_mask3_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5867            a, b, c, 0,
5868        );
5869        assert_eq_m512d(r, c);
5870        let r = _mm512_mask3_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5871            a, b, c, 0b00001111,
5872        );
5873        let e = _mm512_setr_pd(1., -1., 1., -1., -1., -1., -1., -1.);
5874        assert_eq_m512d(r, e);
5875    }
5876
5877    #[simd_test(enable = "avx512f")]
5878    unsafe fn test_mm512_fmsubadd_round_pd() {
5879        let a = _mm512_set1_pd(0.000000000000000007);
5880        let b = _mm512_set1_pd(1.);
5881        let c = _mm512_set1_pd(-1.);
5882        let r =
5883            _mm512_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5884        let e = _mm512_setr_pd(-1., 1., -1., 1., -1., 1., -1., 1.);
5885        assert_eq_m512d(r, e);
5886        let r = _mm512_fmsubadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5887        let e = _mm512_setr_pd(
5888            -0.9999999999999999,
5889            1.,
5890            -0.9999999999999999,
5891            1.,
5892            -0.9999999999999999,
5893            1.,
5894            -0.9999999999999999,
5895            1.,
5896        );
5897        assert_eq_m512d(r, e);
5898    }
5899
5900    #[simd_test(enable = "avx512f")]
5901    unsafe fn test_mm512_mask_fmsubadd_round_pd() {
5902        let a = _mm512_set1_pd(0.000000000000000007);
5903        let b = _mm512_set1_pd(1.);
5904        let c = _mm512_set1_pd(-1.);
5905        let r = _mm512_mask_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5906            a, 0, b, c,
5907        );
5908        assert_eq_m512d(r, a);
5909        let r = _mm512_mask_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5910            a, 0b00001111, b, c,
5911        );
5912        let e = _mm512_setr_pd(
5913            -1.,
5914            1.,
5915            -1.,
5916            1.,
5917            0.000000000000000007,
5918            0.000000000000000007,
5919            0.000000000000000007,
5920            0.000000000000000007,
5921        );
5922        assert_eq_m512d(r, e);
5923    }
5924
5925    #[simd_test(enable = "avx512f")]
5926    unsafe fn test_mm512_maskz_fmsubadd_round_pd() {
5927        let a = _mm512_set1_pd(0.000000000000000007);
5928        let b = _mm512_set1_pd(1.);
5929        let c = _mm512_set1_pd(-1.);
5930        let r = _mm512_maskz_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5931            0, a, b, c,
5932        );
5933        assert_eq_m512d(r, _mm512_setzero_pd());
5934        let r = _mm512_maskz_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5935            0b00001111, a, b, c,
5936        );
5937        let e = _mm512_setr_pd(-1., 1., -1., 1., 0., 0., 0., 0.);
5938        assert_eq_m512d(r, e);
5939    }
5940
5941    #[simd_test(enable = "avx512f")]
5942    unsafe fn test_mm512_mask3_fmsubadd_round_pd() {
5943        let a = _mm512_set1_pd(0.000000000000000007);
5944        let b = _mm512_set1_pd(1.);
5945        let c = _mm512_set1_pd(-1.);
5946        let r = _mm512_mask3_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5947            a, b, c, 0,
5948        );
5949        assert_eq_m512d(r, c);
5950        let r = _mm512_mask3_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5951            a, b, c, 0b00001111,
5952        );
5953        let e = _mm512_setr_pd(-1., 1., -1., 1., -1., -1., -1., -1.);
5954        assert_eq_m512d(r, e);
5955    }
5956
5957    #[simd_test(enable = "avx512f")]
5958    unsafe fn test_mm512_fnmadd_round_pd() {
5959        let a = _mm512_set1_pd(0.000000000000000007);
5960        let b = _mm512_set1_pd(1.);
5961        let c = _mm512_set1_pd(1.);
5962        let r =
5963            _mm512_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5964        let e = _mm512_set1_pd(1.);
5965        assert_eq_m512d(r, e);
5966        let r = _mm512_fnmadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5967        let e = _mm512_set1_pd(0.9999999999999999);
5968        assert_eq_m512d(r, e);
5969    }
5970
5971    #[simd_test(enable = "avx512f")]
5972    unsafe fn test_mm512_mask_fnmadd_round_pd() {
5973        let a = _mm512_set1_pd(0.000000000000000007);
5974        let b = _mm512_set1_pd(1.);
5975        let c = _mm512_set1_pd(1.);
5976        let r = _mm512_mask_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5977            a, 0, b, c,
5978        );
5979        assert_eq_m512d(r, a);
5980        let r = _mm512_mask_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5981            a, 0b00001111, b, c,
5982        );
5983        let e = _mm512_setr_pd(
5984            1.,
5985            1.,
5986            1.,
5987            1.,
5988            0.000000000000000007,
5989            0.000000000000000007,
5990            0.000000000000000007,
5991            0.000000000000000007,
5992        );
5993        assert_eq_m512d(r, e);
5994    }
5995
5996    #[simd_test(enable = "avx512f")]
5997    unsafe fn test_mm512_maskz_fnmadd_round_pd() {
5998        let a = _mm512_set1_pd(0.000000000000000007);
5999        let b = _mm512_set1_pd(1.);
6000        let c = _mm512_set1_pd(1.);
6001        let r = _mm512_maskz_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6002            0, a, b, c,
6003        );
6004        assert_eq_m512d(r, _mm512_setzero_pd());
6005        let r = _mm512_maskz_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6006            0b00001111, a, b, c,
6007        );
6008        let e = _mm512_setr_pd(1., 1., 1., 1., 0., 0., 0., 0.);
6009        assert_eq_m512d(r, e);
6010    }
6011
6012    #[simd_test(enable = "avx512f")]
6013    unsafe fn test_mm512_mask3_fnmadd_round_pd() {
6014        let a = _mm512_set1_pd(0.000000000000000007);
6015        let b = _mm512_set1_pd(1.);
6016        let c = _mm512_set1_pd(1.);
6017        let r = _mm512_mask3_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6018            a, b, c, 0,
6019        );
6020        assert_eq_m512d(r, c);
6021        let r = _mm512_mask3_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6022            a, b, c, 0b00001111,
6023        );
6024        let e = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
6025        assert_eq_m512d(r, e);
6026    }
6027
6028    #[simd_test(enable = "avx512f")]
6029    unsafe fn test_mm512_fnmsub_round_pd() {
6030        let a = _mm512_set1_pd(0.000000000000000007);
6031        let b = _mm512_set1_pd(1.);
6032        let c = _mm512_set1_pd(-1.);
6033        let r =
6034            _mm512_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
6035        let e = _mm512_set1_pd(1.);
6036        assert_eq_m512d(r, e);
6037        let r = _mm512_fnmsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
6038        let e = _mm512_set1_pd(0.9999999999999999);
6039        assert_eq_m512d(r, e);
6040    }
6041
6042    #[simd_test(enable = "avx512f")]
6043    unsafe fn test_mm512_mask_fnmsub_round_pd() {
6044        let a = _mm512_set1_pd(0.000000000000000007);
6045        let b = _mm512_set1_pd(1.);
6046        let c = _mm512_set1_pd(-1.);
6047        let r = _mm512_mask_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6048            a, 0, b, c,
6049        );
6050        assert_eq_m512d(r, a);
6051        let r = _mm512_mask_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6052            a, 0b00001111, b, c,
6053        );
6054        let e = _mm512_setr_pd(
6055            1.,
6056            1.,
6057            1.,
6058            1.,
6059            0.000000000000000007,
6060            0.000000000000000007,
6061            0.000000000000000007,
6062            0.000000000000000007,
6063        );
6064        assert_eq_m512d(r, e);
6065    }
6066
6067    #[simd_test(enable = "avx512f")]
6068    unsafe fn test_mm512_maskz_fnmsub_round_pd() {
6069        let a = _mm512_set1_pd(0.000000000000000007);
6070        let b = _mm512_set1_pd(1.);
6071        let c = _mm512_set1_pd(-1.);
6072        let r = _mm512_maskz_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6073            0, a, b, c,
6074        );
6075        assert_eq_m512d(r, _mm512_setzero_pd());
6076        let r = _mm512_maskz_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6077            0b00001111, a, b, c,
6078        );
6079        let e = _mm512_setr_pd(1., 1., 1., 1., 0., 0., 0., 0.);
6080        assert_eq_m512d(r, e);
6081    }
6082
6083    #[simd_test(enable = "avx512f")]
6084    unsafe fn test_mm512_mask3_fnmsub_round_pd() {
6085        let a = _mm512_set1_pd(0.000000000000000007);
6086        let b = _mm512_set1_pd(1.);
6087        let c = _mm512_set1_pd(-1.);
6088        let r = _mm512_mask3_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6089            a, b, c, 0,
6090        );
6091        assert_eq_m512d(r, c);
6092        let r = _mm512_mask3_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6093            a, b, c, 0b00001111,
6094        );
6095        let e = _mm512_setr_pd(1., 1., 1., 1., -1., -1., -1., -1.);
6096        assert_eq_m512d(r, e);
6097    }
6098
6099    #[simd_test(enable = "avx512f")]
6100    unsafe fn test_mm512_max_round_pd() {
6101        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6102        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6103        let r = _mm512_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, b);
6104        let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
6105        assert_eq_m512d(r, e);
6106    }
6107
6108    #[simd_test(enable = "avx512f")]
6109    unsafe fn test_mm512_mask_max_round_pd() {
6110        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6111        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6112        let r = _mm512_mask_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
6113        assert_eq_m512d(r, a);
6114        let r = _mm512_mask_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b00001111, a, b);
6115        let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
6116        assert_eq_m512d(r, e);
6117    }
6118
6119    #[simd_test(enable = "avx512f")]
6120    unsafe fn test_mm512_maskz_max_round_pd() {
6121        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6122        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6123        let r = _mm512_maskz_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
6124        assert_eq_m512d(r, _mm512_setzero_pd());
6125        let r = _mm512_maskz_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a, b);
6126        let e = _mm512_setr_pd(7., 6., 5., 4., 0., 0., 0., 0.);
6127        assert_eq_m512d(r, e);
6128    }
6129
6130    #[simd_test(enable = "avx512f")]
6131    unsafe fn test_mm512_min_round_pd() {
6132        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6133        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6134        let r = _mm512_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, b);
6135        let e = _mm512_setr_pd(0., 1., 2., 3., 3., 2., 1., 0.);
6136        assert_eq_m512d(r, e);
6137    }
6138
6139    #[simd_test(enable = "avx512f")]
6140    unsafe fn test_mm512_mask_min_round_pd() {
6141        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6142        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6143        let r = _mm512_mask_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
6144        assert_eq_m512d(r, a);
6145        let r = _mm512_mask_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b00001111, a, b);
6146        let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6147        assert_eq_m512d(r, e);
6148    }
6149
6150    #[simd_test(enable = "avx512f")]
6151    unsafe fn test_mm512_maskz_min_round_pd() {
6152        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6153        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6154        let r = _mm512_maskz_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
6155        assert_eq_m512d(r, _mm512_setzero_pd());
6156        let r = _mm512_maskz_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a, b);
6157        let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
6158        assert_eq_m512d(r, e);
6159    }
6160
6161    #[simd_test(enable = "avx512f")]
6162    unsafe fn test_mm512_getexp_round_pd() {
6163        let a = _mm512_set1_pd(3.);
6164        let r = _mm512_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a);
6165        let e = _mm512_set1_pd(1.);
6166        assert_eq_m512d(r, e);
6167    }
6168
6169    #[simd_test(enable = "avx512f")]
6170    unsafe fn test_mm512_mask_getexp_round_pd() {
6171        let a = _mm512_set1_pd(3.);
6172        let r = _mm512_mask_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a);
6173        assert_eq_m512d(r, a);
6174        let r = _mm512_mask_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b11110000, a);
6175        let e = _mm512_setr_pd(3., 3., 3., 3., 1., 1., 1., 1.);
6176        assert_eq_m512d(r, e);
6177    }
6178
6179    #[simd_test(enable = "avx512f")]
6180    unsafe fn test_mm512_maskz_getexp_round_pd() {
6181        let a = _mm512_set1_pd(3.);
6182        let r = _mm512_maskz_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a);
6183        assert_eq_m512d(r, _mm512_setzero_pd());
6184        let r = _mm512_maskz_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b11110000, a);
6185        let e = _mm512_setr_pd(0., 0., 0., 0., 1., 1., 1., 1.);
6186        assert_eq_m512d(r, e);
6187    }
6188
6189    #[simd_test(enable = "avx512f")]
6190    unsafe fn test_mm512_roundscale_round_pd() {
6191        let a = _mm512_set1_pd(1.1);
6192        let r = _mm512_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a);
6193        let e = _mm512_set1_pd(1.0);
6194        assert_eq_m512d(r, e);
6195    }
6196
6197    #[simd_test(enable = "avx512f")]
6198    unsafe fn test_mm512_mask_roundscale_round_pd() {
6199        let a = _mm512_set1_pd(1.1);
6200        let r = _mm512_mask_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a, 0, a);
6201        let e = _mm512_set1_pd(1.1);
6202        assert_eq_m512d(r, e);
6203        let r = _mm512_mask_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a, 0b11111111, a);
6204        let e = _mm512_set1_pd(1.0);
6205        assert_eq_m512d(r, e);
6206    }
6207
6208    #[simd_test(enable = "avx512f")]
6209    unsafe fn test_mm512_maskz_roundscale_round_pd() {
6210        let a = _mm512_set1_pd(1.1);
6211        let r = _mm512_maskz_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(0, a);
6212        assert_eq_m512d(r, _mm512_setzero_pd());
6213        let r = _mm512_maskz_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(0b11111111, a);
6214        let e = _mm512_set1_pd(1.0);
6215        assert_eq_m512d(r, e);
6216    }
6217
6218    #[simd_test(enable = "avx512f")]
6219    unsafe fn test_mm512_scalef_round_pd() {
6220        let a = _mm512_set1_pd(1.);
6221        let b = _mm512_set1_pd(3.);
6222        let r = _mm512_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
6223        let e = _mm512_set1_pd(8.);
6224        assert_eq_m512d(r, e);
6225    }
6226
6227    #[simd_test(enable = "avx512f")]
6228    unsafe fn test_mm512_mask_scalef_round_pd() {
6229        let a = _mm512_set1_pd(1.);
6230        let b = _mm512_set1_pd(3.);
6231        let r = _mm512_mask_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6232            a, 0, a, b,
6233        );
6234        assert_eq_m512d(r, a);
6235        let r = _mm512_mask_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6236            a, 0b11110000, a, b,
6237        );
6238        let e = _mm512_set_pd(8., 8., 8., 8., 1., 1., 1., 1.);
6239        assert_eq_m512d(r, e);
6240    }
6241
6242    #[simd_test(enable = "avx512f")]
6243    unsafe fn test_mm512_maskz_scalef_round_pd() {
6244        let a = _mm512_set1_pd(1.);
6245        let b = _mm512_set1_pd(3.);
6246        let r = _mm512_maskz_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6247            0, a, b,
6248        );
6249        assert_eq_m512d(r, _mm512_setzero_pd());
6250        let r = _mm512_maskz_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6251            0b11110000, a, b,
6252        );
6253        let e = _mm512_set_pd(8., 8., 8., 8., 0., 0., 0., 0.);
6254        assert_eq_m512d(r, e);
6255    }
6256
6257    #[simd_test(enable = "avx512f")]
6258    unsafe fn test_mm512_fixupimm_round_pd() {
6259        let a = _mm512_set1_pd(f64::NAN);
6260        let b = _mm512_set1_pd(f64::MAX);
6261        let c = _mm512_set1_epi64(i32::MAX as i64);
6262        let r = _mm512_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(a, b, c);
6263        let e = _mm512_set1_pd(0.0);
6264        assert_eq_m512d(r, e);
6265    }
6266
6267    #[simd_test(enable = "avx512f")]
6268    unsafe fn test_mm512_mask_fixupimm_round_pd() {
6269        let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
6270        let b = _mm512_set1_pd(f64::MAX);
6271        let c = _mm512_set1_epi64(i32::MAX as i64);
6272        let r = _mm512_mask_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(a, 0b11110000, b, c);
6273        let e = _mm512_set_pd(0., 0., 0., 0., 1., 1., 1., 1.);
6274        assert_eq_m512d(r, e);
6275    }
6276
6277    #[simd_test(enable = "avx512f")]
6278    unsafe fn test_mm512_maskz_fixupimm_round_pd() {
6279        let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
6280        let b = _mm512_set1_pd(f64::MAX);
6281        let c = _mm512_set1_epi64(i32::MAX as i64);
6282        let r = _mm512_maskz_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(0b11110000, a, b, c);
6283        let e = _mm512_set_pd(0., 0., 0., 0., 0., 0., 0., 0.);
6284        assert_eq_m512d(r, e);
6285    }
6286
6287    #[simd_test(enable = "avx512f")]
6288    unsafe fn test_mm512_getmant_round_pd() {
6289        let a = _mm512_set1_pd(10.);
6290        let r = _mm512_getmant_round_pd::<
6291            _MM_MANT_NORM_1_2,
6292            _MM_MANT_SIGN_SRC,
6293            _MM_FROUND_CUR_DIRECTION,
6294        >(a);
6295        let e = _mm512_set1_pd(1.25);
6296        assert_eq_m512d(r, e);
6297    }
6298
6299    #[simd_test(enable = "avx512f")]
6300    unsafe fn test_mm512_mask_getmant_round_pd() {
6301        let a = _mm512_set1_pd(10.);
6302        let r = _mm512_mask_getmant_round_pd::<
6303            _MM_MANT_NORM_1_2,
6304            _MM_MANT_SIGN_SRC,
6305            _MM_FROUND_CUR_DIRECTION,
6306        >(a, 0, a);
6307        assert_eq_m512d(r, a);
6308        let r = _mm512_mask_getmant_round_pd::<
6309            _MM_MANT_NORM_1_2,
6310            _MM_MANT_SIGN_SRC,
6311            _MM_FROUND_CUR_DIRECTION,
6312        >(a, 0b11110000, a);
6313        let e = _mm512_setr_pd(10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25);
6314        assert_eq_m512d(r, e);
6315    }
6316
6317    #[simd_test(enable = "avx512f")]
6318    unsafe fn test_mm512_maskz_getmant_round_pd() {
6319        let a = _mm512_set1_pd(10.);
6320        let r = _mm512_maskz_getmant_round_pd::<
6321            _MM_MANT_NORM_1_2,
6322            _MM_MANT_SIGN_SRC,
6323            _MM_FROUND_CUR_DIRECTION,
6324        >(0, a);
6325        assert_eq_m512d(r, _mm512_setzero_pd());
6326        let r = _mm512_maskz_getmant_round_pd::<
6327            _MM_MANT_NORM_1_2,
6328            _MM_MANT_SIGN_SRC,
6329            _MM_FROUND_CUR_DIRECTION,
6330        >(0b11110000, a);
6331        let e = _mm512_setr_pd(0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25);
6332        assert_eq_m512d(r, e);
6333    }
6334
6335    #[simd_test(enable = "avx512f")]
6336    unsafe fn test_mm512_cvt_roundps_pd() {
6337        let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6338        let r = _mm512_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(a);
6339        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6340        assert_eq_m512d(r, e);
6341    }
6342
6343    #[simd_test(enable = "avx512f")]
6344    unsafe fn test_mm512_mask_cvt_roundps_pd() {
6345        let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6346        let src = _mm512_set1_pd(0.);
6347        let r = _mm512_mask_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6348        assert_eq_m512d(r, src);
6349        let r = _mm512_mask_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6350        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6351        assert_eq_m512d(r, e);
6352    }
6353
6354    #[simd_test(enable = "avx512f")]
6355    unsafe fn test_mm512_maskz_cvt_roundps_pd() {
6356        let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6357        let r = _mm512_maskz_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(0, a);
6358        assert_eq_m512d(r, _mm512_setzero_pd());
6359        let r = _mm512_maskz_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6360        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6361        assert_eq_m512d(r, e);
6362    }
6363
6364    #[simd_test(enable = "avx512f")]
6365    unsafe fn test_mm512_cvt_roundpd_ps() {
6366        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6367        let r = _mm512_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(a);
6368        let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6369        assert_eq_m256(r, e);
6370    }
6371
6372    #[simd_test(enable = "avx512f")]
6373    unsafe fn test_mm512_mask_cvt_roundpd_ps() {
6374        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6375        let src = _mm256_set1_ps(0.);
6376        let r = _mm512_mask_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6377        assert_eq_m256(r, src);
6378        let r = _mm512_mask_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6379        let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6380        assert_eq_m256(r, e);
6381    }
6382
6383    #[simd_test(enable = "avx512f")]
6384    unsafe fn test_mm512_maskz_cvt_roundpd_ps() {
6385        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6386        let r = _mm512_maskz_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(0, a);
6387        assert_eq_m256(r, _mm256_setzero_ps());
6388        let r = _mm512_maskz_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6389        let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6390        assert_eq_m256(r, e);
6391    }
6392
6393    #[simd_test(enable = "avx512f")]
6394    unsafe fn test_mm512_cvt_roundpd_epi32() {
6395        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6396        let r = _mm512_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(a);
6397        let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
6398        assert_eq_m256i(r, e);
6399    }
6400
6401    #[simd_test(enable = "avx512f")]
6402    unsafe fn test_mm512_mask_cvt_roundpd_epi32() {
6403        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6404        let src = _mm256_set1_epi32(0);
6405        let r = _mm512_mask_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6406        assert_eq_m256i(r, src);
6407        let r = _mm512_mask_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6408        let e = _mm256_setr_epi32(0, -2, 2, -4, 0, 0, 0, 0);
6409        assert_eq_m256i(r, e);
6410    }
6411
6412    #[simd_test(enable = "avx512f")]
6413    unsafe fn test_mm512_maskz_cvt_roundpd_epi32() {
6414        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6415        let r = _mm512_maskz_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(0, a);
6416        assert_eq_m256i(r, _mm256_setzero_si256());
6417        let r = _mm512_maskz_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6418        let e = _mm256_setr_epi32(0, -2, 2, -4, 0, 0, 0, 0);
6419        assert_eq_m256i(r, e);
6420    }
6421
6422    #[simd_test(enable = "avx512f")]
6423    unsafe fn test_mm512_cvt_roundpd_epu32() {
6424        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6425        let r = _mm512_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(a);
6426        let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
6427        assert_eq_m256i(r, e);
6428    }
6429
6430    #[simd_test(enable = "avx512f")]
6431    unsafe fn test_mm512_mask_cvt_roundpd_epu32() {
6432        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6433        let src = _mm256_set1_epi32(0);
6434        let r = _mm512_mask_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6435        assert_eq_m256i(r, src);
6436        let r = _mm512_mask_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6437        let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
6438        assert_eq_m256i(r, e);
6439    }
6440
6441    #[simd_test(enable = "avx512f")]
6442    unsafe fn test_mm512_maskz_cvt_roundpd_epu32() {
6443        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6444        let r = _mm512_maskz_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(0, a);
6445        assert_eq_m256i(r, _mm256_setzero_si256());
6446        let r = _mm512_maskz_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6447        let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
6448        assert_eq_m256i(r, e);
6449    }
6450
6451    #[simd_test(enable = "avx512f")]
6452    unsafe fn test_mm512_setzero_pd() {
6453        assert_eq_m512d(_mm512_setzero_pd(), _mm512_set1_pd(0.));
6454    }
6455
6456    #[simd_test(enable = "avx512f")]
6457    unsafe fn test_mm512_set1_epi64() {
6458        let r = _mm512_set_epi64(2, 2, 2, 2, 2, 2, 2, 2);
6459        assert_eq_m512i(r, _mm512_set1_epi64(2));
6460    }
6461
6462    #[simd_test(enable = "avx512f")]
6463    unsafe fn test_mm512_set1_pd() {
6464        let expected = _mm512_set_pd(2., 2., 2., 2., 2., 2., 2., 2.);
6465        assert_eq_m512d(expected, _mm512_set1_pd(2.));
6466    }
6467
6468    #[simd_test(enable = "avx512f")]
6469    unsafe fn test_mm512_set4_epi64() {
6470        let r = _mm512_set_epi64(4, 3, 2, 1, 4, 3, 2, 1);
6471        assert_eq_m512i(r, _mm512_set4_epi64(4, 3, 2, 1));
6472    }
6473
6474    #[simd_test(enable = "avx512f")]
6475    unsafe fn test_mm512_set4_pd() {
6476        let r = _mm512_set_pd(4., 3., 2., 1., 4., 3., 2., 1.);
6477        assert_eq_m512d(r, _mm512_set4_pd(4., 3., 2., 1.));
6478    }
6479
6480    #[simd_test(enable = "avx512f")]
6481    unsafe fn test_mm512_setr4_epi64() {
6482        let r = _mm512_set_epi64(4, 3, 2, 1, 4, 3, 2, 1);
6483        assert_eq_m512i(r, _mm512_setr4_epi64(1, 2, 3, 4));
6484    }
6485
6486    #[simd_test(enable = "avx512f")]
6487    unsafe fn test_mm512_setr4_pd() {
6488        let r = _mm512_set_pd(4., 3., 2., 1., 4., 3., 2., 1.);
6489        assert_eq_m512d(r, _mm512_setr4_pd(1., 2., 3., 4.));
6490    }
6491
6492    #[simd_test(enable = "avx512f")]
6493    unsafe fn test_mm512_cmplt_pd_mask() {
6494        #[rustfmt::skip]
6495        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6496        let b = _mm512_set1_pd(-1.);
6497        let m = _mm512_cmplt_pd_mask(a, b);
6498        assert_eq!(m, 0b00000101);
6499    }
6500
6501    #[simd_test(enable = "avx512f")]
6502    unsafe fn test_mm512_mask_cmplt_pd_mask() {
6503        #[rustfmt::skip]
6504        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6505        let b = _mm512_set1_pd(-1.);
6506        let mask = 0b01100110;
6507        let r = _mm512_mask_cmplt_pd_mask(mask, a, b);
6508        assert_eq!(r, 0b00000100);
6509    }
6510
6511    #[simd_test(enable = "avx512f")]
6512    unsafe fn test_mm512_cmpnlt_pd_mask() {
6513        #[rustfmt::skip]
6514        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6515        let b = _mm512_set1_pd(-1.);
6516        assert_eq!(_mm512_cmpnlt_pd_mask(a, b), !_mm512_cmplt_pd_mask(a, b));
6517    }
6518
6519    #[simd_test(enable = "avx512f")]
6520    unsafe fn test_mm512_mask_cmpnlt_pd_mask() {
6521        #[rustfmt::skip]
6522        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6523        let b = _mm512_set1_pd(-1.);
6524        let mask = 0b01111010;
6525        assert_eq!(_mm512_mask_cmpnlt_pd_mask(mask, a, b), 0b01111010);
6526    }
6527
6528    #[simd_test(enable = "avx512f")]
6529    unsafe fn test_mm512_cmple_pd_mask() {
6530        #[rustfmt::skip]
6531        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6532        let b = _mm512_set1_pd(-1.);
6533        assert_eq!(_mm512_cmple_pd_mask(a, b), 0b00100101);
6534    }
6535
6536    #[simd_test(enable = "avx512f")]
6537    unsafe fn test_mm512_mask_cmple_pd_mask() {
6538        #[rustfmt::skip]
6539        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6540        let b = _mm512_set1_pd(-1.);
6541        let mask = 0b01111010;
6542        assert_eq!(_mm512_mask_cmple_pd_mask(mask, a, b), 0b00100000);
6543    }
6544
6545    #[simd_test(enable = "avx512f")]
6546    unsafe fn test_mm512_cmpnle_pd_mask() {
6547        #[rustfmt::skip]
6548        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6549        let b = _mm512_set1_pd(-1.);
6550        let m = _mm512_cmpnle_pd_mask(b, a);
6551        assert_eq!(m, 0b00001101);
6552    }
6553
6554    #[simd_test(enable = "avx512f")]
6555    unsafe fn test_mm512_mask_cmpnle_pd_mask() {
6556        #[rustfmt::skip]
6557        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6558        let b = _mm512_set1_pd(-1.);
6559        let mask = 0b01100110;
6560        let r = _mm512_mask_cmpnle_pd_mask(mask, b, a);
6561        assert_eq!(r, 0b00000100);
6562    }
6563
6564    #[simd_test(enable = "avx512f")]
6565    unsafe fn test_mm512_cmpeq_pd_mask() {
6566        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6567        let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6568        let m = _mm512_cmpeq_pd_mask(b, a);
6569        assert_eq!(m, 0b11001101);
6570    }
6571
6572    #[simd_test(enable = "avx512f")]
6573    unsafe fn test_mm512_mask_cmpeq_pd_mask() {
6574        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6575        let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6576        let mask = 0b01111010;
6577        let r = _mm512_mask_cmpeq_pd_mask(mask, b, a);
6578        assert_eq!(r, 0b01001000);
6579    }
6580
6581    #[simd_test(enable = "avx512f")]
6582    unsafe fn test_mm512_cmpneq_pd_mask() {
6583        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6584        let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6585        let m = _mm512_cmpneq_pd_mask(b, a);
6586        assert_eq!(m, 0b00110010);
6587    }
6588
6589    #[simd_test(enable = "avx512f")]
6590    unsafe fn test_mm512_mask_cmpneq_pd_mask() {
6591        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6592        let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6593        let mask = 0b01111010;
6594        let r = _mm512_mask_cmpneq_pd_mask(mask, b, a);
6595        assert_eq!(r, 0b00110010)
6596    }
6597
6598    #[simd_test(enable = "avx512f")]
6599    unsafe fn test_mm512_cmp_pd_mask() {
6600        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6601        let b = _mm512_set1_pd(-1.);
6602        let m = _mm512_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6603        assert_eq!(m, 0b00000101);
6604    }
6605
6606    #[simd_test(enable = "avx512f")]
6607    unsafe fn test_mm512_mask_cmp_pd_mask() {
6608        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6609        let b = _mm512_set1_pd(-1.);
6610        let mask = 0b01100110;
6611        let r = _mm512_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6612        assert_eq!(r, 0b00000100);
6613    }
6614
6615    #[simd_test(enable = "avx512f,avx512vl")]
6616    unsafe fn test_mm256_cmp_pd_mask() {
6617        let a = _mm256_set_pd(0., 1., -1., 13.);
6618        let b = _mm256_set1_pd(1.);
6619        let m = _mm256_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6620        assert_eq!(m, 0b00001010);
6621    }
6622
6623    #[simd_test(enable = "avx512f,avx512vl")]
6624    unsafe fn test_mm256_mask_cmp_pd_mask() {
6625        let a = _mm256_set_pd(0., 1., -1., 13.);
6626        let b = _mm256_set1_pd(1.);
6627        let mask = 0b11111111;
6628        let r = _mm256_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6629        assert_eq!(r, 0b00001010);
6630    }
6631
6632    #[simd_test(enable = "avx512f,avx512vl")]
6633    unsafe fn test_mm_cmp_pd_mask() {
6634        let a = _mm_set_pd(0., 1.);
6635        let b = _mm_set1_pd(1.);
6636        let m = _mm_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6637        assert_eq!(m, 0b00000010);
6638    }
6639
6640    #[simd_test(enable = "avx512f,avx512vl")]
6641    unsafe fn test_mm_mask_cmp_pd_mask() {
6642        let a = _mm_set_pd(0., 1.);
6643        let b = _mm_set1_pd(1.);
6644        let mask = 0b11111111;
6645        let r = _mm_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6646        assert_eq!(r, 0b00000010);
6647    }
6648
6649    #[simd_test(enable = "avx512f")]
6650    unsafe fn test_mm512_cmp_round_pd_mask() {
6651        #[rustfmt::skip]
6652        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6653        let b = _mm512_set1_pd(-1.);
6654        let m = _mm512_cmp_round_pd_mask::<_CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION>(a, b);
6655        assert_eq!(m, 0b00000101);
6656    }
6657
6658    #[simd_test(enable = "avx512f")]
6659    unsafe fn test_mm512_mask_cmp_round_pd_mask() {
6660        #[rustfmt::skip]
6661        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6662        let b = _mm512_set1_pd(-1.);
6663        let mask = 0b01100110;
6664        let r = _mm512_mask_cmp_round_pd_mask::<_CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION>(mask, a, b);
6665        assert_eq!(r, 0b00000100);
6666    }
6667
6668    #[simd_test(enable = "avx512f")]
6669    unsafe fn test_mm512_cmpord_pd_mask() {
6670        #[rustfmt::skip]
6671        let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6672        #[rustfmt::skip]
6673        let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6674        let m = _mm512_cmpord_pd_mask(a, b);
6675        assert_eq!(m, 0b00000101);
6676    }
6677
6678    #[simd_test(enable = "avx512f")]
6679    unsafe fn test_mm512_mask_cmpord_pd_mask() {
6680        #[rustfmt::skip]
6681        let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6682        #[rustfmt::skip]
6683        let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6684        let mask = 0b11000011;
6685        let m = _mm512_mask_cmpord_pd_mask(mask, a, b);
6686        assert_eq!(m, 0b00000001);
6687    }
6688
6689    #[simd_test(enable = "avx512f")]
6690    unsafe fn test_mm512_cmpunord_pd_mask() {
6691        #[rustfmt::skip]
6692        let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6693        #[rustfmt::skip]
6694        let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6695        let m = _mm512_cmpunord_pd_mask(a, b);
6696
6697        assert_eq!(m, 0b11111010);
6698    }
6699
6700    #[simd_test(enable = "avx512f")]
6701    unsafe fn test_mm512_mask_cmpunord_pd_mask() {
6702        #[rustfmt::skip]
6703        let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6704        #[rustfmt::skip]
6705        let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6706        let mask = 0b00001111;
6707        let m = _mm512_mask_cmpunord_pd_mask(mask, a, b);
6708        assert_eq!(m, 0b000001010);
6709    }
6710
6711    #[simd_test(enable = "avx512f")]
6712    unsafe fn test_mm512_cmplt_epu64_mask() {
6713        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6714        let b = _mm512_set1_epi64(-1);
6715        let m = _mm512_cmplt_epu64_mask(a, b);
6716        assert_eq!(m, 0b11001111);
6717    }
6718
6719    #[simd_test(enable = "avx512f")]
6720    unsafe fn test_mm512_mask_cmplt_epu64_mask() {
6721        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6722        let b = _mm512_set1_epi64(-1);
6723        let mask = 0b01111010;
6724        let r = _mm512_mask_cmplt_epu64_mask(mask, a, b);
6725        assert_eq!(r, 0b01001010);
6726    }
6727
6728    #[simd_test(enable = "avx512f,avx512vl")]
6729    unsafe fn test_mm256_cmplt_epu64_mask() {
6730        let a = _mm256_set_epi64x(0, 1, 2, 100);
6731        let b = _mm256_set1_epi64x(2);
6732        let r = _mm256_cmplt_epu64_mask(a, b);
6733        assert_eq!(r, 0b00001100);
6734    }
6735
6736    #[simd_test(enable = "avx512f,avx512vl")]
6737    unsafe fn test_mm256_mask_cmplt_epu64_mask() {
6738        let a = _mm256_set_epi64x(0, 1, 2, 100);
6739        let b = _mm256_set1_epi64x(2);
6740        let mask = 0b11111111;
6741        let r = _mm256_mask_cmplt_epu64_mask(mask, a, b);
6742        assert_eq!(r, 0b00001100);
6743    }
6744
6745    #[simd_test(enable = "avx512f,avx512vl")]
6746    unsafe fn test_mm_cmplt_epu64_mask() {
6747        let a = _mm_set_epi64x(0, 1);
6748        let b = _mm_set1_epi64x(2);
6749        let r = _mm_cmplt_epu64_mask(a, b);
6750        assert_eq!(r, 0b00000011);
6751    }
6752
6753    #[simd_test(enable = "avx512f,avx512vl")]
6754    unsafe fn test_mm_mask_cmplt_epu64_mask() {
6755        let a = _mm_set_epi64x(0, 1);
6756        let b = _mm_set1_epi64x(2);
6757        let mask = 0b11111111;
6758        let r = _mm_mask_cmplt_epu64_mask(mask, a, b);
6759        assert_eq!(r, 0b00000011);
6760    }
6761
6762    #[simd_test(enable = "avx512f")]
6763    unsafe fn test_mm512_cmpgt_epu64_mask() {
6764        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6765        let b = _mm512_set1_epi64(-1);
6766        let m = _mm512_cmpgt_epu64_mask(b, a);
6767        assert_eq!(m, 0b11001111);
6768    }
6769
6770    #[simd_test(enable = "avx512f")]
6771    unsafe fn test_mm512_mask_cmpgt_epu64_mask() {
6772        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6773        let b = _mm512_set1_epi64(-1);
6774        let mask = 0b01111010;
6775        let r = _mm512_mask_cmpgt_epu64_mask(mask, b, a);
6776        assert_eq!(r, 0b01001010);
6777    }
6778
6779    #[simd_test(enable = "avx512f,avx512vl")]
6780    unsafe fn test_mm256_cmpgt_epu64_mask() {
6781        let a = _mm256_set_epi64x(0, 1, 2, 3);
6782        let b = _mm256_set1_epi64x(1);
6783        let r = _mm256_cmpgt_epu64_mask(a, b);
6784        assert_eq!(r, 0b00000011);
6785    }
6786
6787    #[simd_test(enable = "avx512f,avx512vl")]
6788    unsafe fn test_mm256_mask_cmpgt_epu64_mask() {
6789        let a = _mm256_set_epi64x(0, 1, 2, 3);
6790        let b = _mm256_set1_epi64x(1);
6791        let mask = 0b11111111;
6792        let r = _mm256_mask_cmpgt_epu64_mask(mask, a, b);
6793        assert_eq!(r, 0b00000011);
6794    }
6795
6796    #[simd_test(enable = "avx512f,avx512vl")]
6797    unsafe fn test_mm_cmpgt_epu64_mask() {
6798        let a = _mm_set_epi64x(1, 2);
6799        let b = _mm_set1_epi64x(1);
6800        let r = _mm_cmpgt_epu64_mask(a, b);
6801        assert_eq!(r, 0b00000001);
6802    }
6803
6804    #[simd_test(enable = "avx512f,avx512vl")]
6805    unsafe fn test_mm_mask_cmpgt_epu64_mask() {
6806        let a = _mm_set_epi64x(1, 2);
6807        let b = _mm_set1_epi64x(1);
6808        let mask = 0b11111111;
6809        let r = _mm_mask_cmpgt_epu64_mask(mask, a, b);
6810        assert_eq!(r, 0b00000001);
6811    }
6812
6813    #[simd_test(enable = "avx512f")]
6814    unsafe fn test_mm512_cmple_epu64_mask() {
6815        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6816        let b = _mm512_set1_epi64(-1);
6817        assert_eq!(
6818            _mm512_cmple_epu64_mask(a, b),
6819            !_mm512_cmpgt_epu64_mask(a, b)
6820        )
6821    }
6822
6823    #[simd_test(enable = "avx512f")]
6824    unsafe fn test_mm512_mask_cmple_epu64_mask() {
6825        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6826        let b = _mm512_set1_epi64(-1);
6827        let mask = 0b01111010;
6828        assert_eq!(_mm512_mask_cmple_epu64_mask(mask, a, b), 0b01111010);
6829    }
6830
6831    #[simd_test(enable = "avx512f,avx512vl")]
6832    unsafe fn test_mm256_cmple_epu64_mask() {
6833        let a = _mm256_set_epi64x(0, 1, 2, 1);
6834        let b = _mm256_set1_epi64x(1);
6835        let r = _mm256_cmple_epu64_mask(a, b);
6836        assert_eq!(r, 0b00001101)
6837    }
6838
6839    #[simd_test(enable = "avx512f,avx512vl")]
6840    unsafe fn test_mm256_mask_cmple_epu64_mask() {
6841        let a = _mm256_set_epi64x(0, 1, 2, 1);
6842        let b = _mm256_set1_epi64x(1);
6843        let mask = 0b11111111;
6844        let r = _mm256_mask_cmple_epu64_mask(mask, a, b);
6845        assert_eq!(r, 0b00001101)
6846    }
6847
6848    #[simd_test(enable = "avx512f,avx512vl")]
6849    unsafe fn test_mm_cmple_epu64_mask() {
6850        let a = _mm_set_epi64x(0, 1);
6851        let b = _mm_set1_epi64x(1);
6852        let r = _mm_cmple_epu64_mask(a, b);
6853        assert_eq!(r, 0b00000011)
6854    }
6855
6856    #[simd_test(enable = "avx512f,avx512vl")]
6857    unsafe fn test_mm_mask_cmple_epu64_mask() {
6858        let a = _mm_set_epi64x(0, 1);
6859        let b = _mm_set1_epi64x(1);
6860        let mask = 0b11111111;
6861        let r = _mm_mask_cmple_epu64_mask(mask, a, b);
6862        assert_eq!(r, 0b00000011)
6863    }
6864
6865    #[simd_test(enable = "avx512f")]
6866    unsafe fn test_mm512_cmpge_epu64_mask() {
6867        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6868        let b = _mm512_set1_epi64(-1);
6869        assert_eq!(
6870            _mm512_cmpge_epu64_mask(a, b),
6871            !_mm512_cmplt_epu64_mask(a, b)
6872        );
6873    }
6874
6875    #[simd_test(enable = "avx512f")]
6876    unsafe fn test_mm512_mask_cmpge_epu64_mask() {
6877        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6878        let b = _mm512_set1_epi64(-1);
6879        let mask = 0b11111111;
6880        let r = _mm512_mask_cmpge_epu64_mask(mask, a, b);
6881        assert_eq!(r, 0b00110000);
6882    }
6883
6884    #[simd_test(enable = "avx512f,avx512vl")]
6885    unsafe fn test_mm256_cmpge_epu64_mask() {
6886        let a = _mm256_set_epi64x(0, 1, 2, u64::MAX as i64);
6887        let b = _mm256_set1_epi64x(1);
6888        let r = _mm256_cmpge_epu64_mask(a, b);
6889        assert_eq!(r, 0b00000111);
6890    }
6891
6892    #[simd_test(enable = "avx512f,avx512vl")]
6893    unsafe fn test_mm256_mask_cmpge_epu64_mask() {
6894        let a = _mm256_set_epi64x(0, 1, 2, u64::MAX as i64);
6895        let b = _mm256_set1_epi64x(1);
6896        let mask = 0b11111111;
6897        let r = _mm256_mask_cmpge_epu64_mask(mask, a, b);
6898        assert_eq!(r, 0b00000111);
6899    }
6900
6901    #[simd_test(enable = "avx512f,avx512vl")]
6902    unsafe fn test_mm_cmpge_epu64_mask() {
6903        let a = _mm_set_epi64x(0, 1);
6904        let b = _mm_set1_epi64x(1);
6905        let r = _mm_cmpge_epu64_mask(a, b);
6906        assert_eq!(r, 0b00000001);
6907    }
6908
6909    #[simd_test(enable = "avx512f,avx512vl")]
6910    unsafe fn test_mm_mask_cmpge_epu64_mask() {
6911        let a = _mm_set_epi64x(0, 1);
6912        let b = _mm_set1_epi64x(1);
6913        let mask = 0b11111111;
6914        let r = _mm_mask_cmpge_epu64_mask(mask, a, b);
6915        assert_eq!(r, 0b00000001);
6916    }
6917
6918    #[simd_test(enable = "avx512f")]
6919    unsafe fn test_mm512_cmpeq_epu64_mask() {
6920        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6921        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6922        let m = _mm512_cmpeq_epu64_mask(b, a);
6923        assert_eq!(m, 0b11001111);
6924    }
6925
6926    #[simd_test(enable = "avx512f")]
6927    unsafe fn test_mm512_mask_cmpeq_epu64_mask() {
6928        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6929        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6930        let mask = 0b01111010;
6931        let r = _mm512_mask_cmpeq_epu64_mask(mask, b, a);
6932        assert_eq!(r, 0b01001010);
6933    }
6934
6935    #[simd_test(enable = "avx512f,avx512vl")]
6936    unsafe fn test_mm256_cmpeq_epu64_mask() {
6937        let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6938        let b = _mm256_set_epi64x(0, 1, 13, 42);
6939        let m = _mm256_cmpeq_epu64_mask(b, a);
6940        assert_eq!(m, 0b00001100);
6941    }
6942
6943    #[simd_test(enable = "avx512f,avx512vl")]
6944    unsafe fn test_mm256_mask_cmpeq_epu64_mask() {
6945        let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6946        let b = _mm256_set_epi64x(0, 1, 13, 42);
6947        let mask = 0b11111111;
6948        let r = _mm256_mask_cmpeq_epu64_mask(mask, b, a);
6949        assert_eq!(r, 0b00001100);
6950    }
6951
6952    #[simd_test(enable = "avx512f,avx512vl")]
6953    unsafe fn test_mm_cmpeq_epu64_mask() {
6954        let a = _mm_set_epi64x(0, 1);
6955        let b = _mm_set_epi64x(0, 1);
6956        let m = _mm_cmpeq_epu64_mask(b, a);
6957        assert_eq!(m, 0b00000011);
6958    }
6959
6960    #[simd_test(enable = "avx512f,avx512vl")]
6961    unsafe fn test_mm_mask_cmpeq_epu64_mask() {
6962        let a = _mm_set_epi64x(0, 1);
6963        let b = _mm_set_epi64x(0, 1);
6964        let mask = 0b11111111;
6965        let r = _mm_mask_cmpeq_epu64_mask(mask, b, a);
6966        assert_eq!(r, 0b00000011);
6967    }
6968
6969    #[simd_test(enable = "avx512f")]
6970    unsafe fn test_mm512_cmpneq_epu64_mask() {
6971        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6972        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6973        let m = _mm512_cmpneq_epu64_mask(b, a);
6974        assert_eq!(m, !_mm512_cmpeq_epu64_mask(b, a));
6975    }
6976
6977    #[simd_test(enable = "avx512f")]
6978    unsafe fn test_mm512_mask_cmpneq_epu64_mask() {
6979        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, -100, 100);
6980        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6981        let mask = 0b01111010;
6982        let r = _mm512_mask_cmpneq_epu64_mask(mask, b, a);
6983        assert_eq!(r, 0b00110010);
6984    }
6985
6986    #[simd_test(enable = "avx512f,avx512vl")]
6987    unsafe fn test_mm256_cmpneq_epu64_mask() {
6988        let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6989        let b = _mm256_set_epi64x(0, 1, 13, 42);
6990        let r = _mm256_cmpneq_epu64_mask(b, a);
6991        assert_eq!(r, 0b00000011);
6992    }
6993
6994    #[simd_test(enable = "avx512f,avx512vl")]
6995    unsafe fn test_mm256_mask_cmpneq_epu64_mask() {
6996        let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6997        let b = _mm256_set_epi64x(0, 1, 13, 42);
6998        let mask = 0b11111111;
6999        let r = _mm256_mask_cmpneq_epu64_mask(mask, b, a);
7000        assert_eq!(r, 0b00000011);
7001    }
7002
7003    #[simd_test(enable = "avx512f,avx512vl")]
7004    unsafe fn test_mm_cmpneq_epu64_mask() {
7005        let a = _mm_set_epi64x(-1, u64::MAX as i64);
7006        let b = _mm_set_epi64x(13, 42);
7007        let r = _mm_cmpneq_epu64_mask(b, a);
7008        assert_eq!(r, 0b00000011);
7009    }
7010
7011    #[simd_test(enable = "avx512f,avx512vl")]
7012    unsafe fn test_mm_mask_cmpneq_epu64_mask() {
7013        let a = _mm_set_epi64x(-1, u64::MAX as i64);
7014        let b = _mm_set_epi64x(13, 42);
7015        let mask = 0b11111111;
7016        let r = _mm_mask_cmpneq_epu64_mask(mask, b, a);
7017        assert_eq!(r, 0b00000011);
7018    }
7019
7020    #[simd_test(enable = "avx512f")]
7021    unsafe fn test_mm512_cmp_epu64_mask() {
7022        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7023        let b = _mm512_set1_epi64(-1);
7024        let m = _mm512_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
7025        assert_eq!(m, 0b11001111);
7026    }
7027
7028    #[simd_test(enable = "avx512f")]
7029    unsafe fn test_mm512_mask_cmp_epu64_mask() {
7030        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7031        let b = _mm512_set1_epi64(-1);
7032        let mask = 0b01111010;
7033        let r = _mm512_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
7034        assert_eq!(r, 0b01001010);
7035    }
7036
7037    #[simd_test(enable = "avx512f,avx512vl")]
7038    unsafe fn test_mm256_cmp_epu64_mask() {
7039        let a = _mm256_set_epi64x(0, 1, -1, 100);
7040        let b = _mm256_set1_epi64x(1);
7041        let m = _mm256_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
7042        assert_eq!(m, 0b00001000);
7043    }
7044
7045    #[simd_test(enable = "avx512f,avx512vl")]
7046    unsafe fn test_mm256_mask_cmp_epu64_mask() {
7047        let a = _mm256_set_epi64x(0, 1, -1, 100);
7048        let b = _mm256_set1_epi64x(1);
7049        let mask = 0b11111111;
7050        let r = _mm256_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
7051        assert_eq!(r, 0b00001000);
7052    }
7053
7054    #[simd_test(enable = "avx512f,avx512vl")]
7055    unsafe fn test_mm_cmp_epu64_mask() {
7056        let a = _mm_set_epi64x(0, 1);
7057        let b = _mm_set1_epi64x(1);
7058        let m = _mm_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
7059        assert_eq!(m, 0b00000010);
7060    }
7061
7062    #[simd_test(enable = "avx512f,avx512vl")]
7063    unsafe fn test_mm_mask_cmp_epu64_mask() {
7064        let a = _mm_set_epi64x(0, 1);
7065        let b = _mm_set1_epi64x(1);
7066        let mask = 0b11111111;
7067        let r = _mm_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
7068        assert_eq!(r, 0b00000010);
7069    }
7070
7071    #[simd_test(enable = "avx512f")]
7072    unsafe fn test_mm512_cmplt_epi64_mask() {
7073        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7074        let b = _mm512_set1_epi64(-1);
7075        let m = _mm512_cmplt_epi64_mask(a, b);
7076        assert_eq!(m, 0b00000101);
7077    }
7078
7079    #[simd_test(enable = "avx512f")]
7080    unsafe fn test_mm512_mask_cmplt_epi64_mask() {
7081        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7082        let b = _mm512_set1_epi64(-1);
7083        let mask = 0b01100110;
7084        let r = _mm512_mask_cmplt_epi64_mask(mask, a, b);
7085        assert_eq!(r, 0b00000100);
7086    }
7087
7088    #[simd_test(enable = "avx512f,avx512vl")]
7089    unsafe fn test_mm256_cmplt_epi64_mask() {
7090        let a = _mm256_set_epi64x(0, 1, -1, -13);
7091        let b = _mm256_set1_epi64x(-1);
7092        let r = _mm256_cmplt_epi64_mask(a, b);
7093        assert_eq!(r, 0b00000001);
7094    }
7095
7096    #[simd_test(enable = "avx512f,avx512vl")]
7097    unsafe fn test_mm256_mask_cmplt_epi64_mask() {
7098        let a = _mm256_set_epi64x(0, 1, -1, -13);
7099        let b = _mm256_set1_epi64x(-1);
7100        let mask = 0b11111111;
7101        let r = _mm256_mask_cmplt_epi64_mask(mask, a, b);
7102        assert_eq!(r, 0b00000001);
7103    }
7104
7105    #[simd_test(enable = "avx512f,avx512vl")]
7106    unsafe fn test_mm_cmplt_epi64_mask() {
7107        let a = _mm_set_epi64x(-1, -13);
7108        let b = _mm_set1_epi64x(-1);
7109        let r = _mm_cmplt_epi64_mask(a, b);
7110        assert_eq!(r, 0b00000001);
7111    }
7112
7113    #[simd_test(enable = "avx512f,avx512vl")]
7114    unsafe fn test_mm_mask_cmplt_epi64_mask() {
7115        let a = _mm_set_epi64x(-1, -13);
7116        let b = _mm_set1_epi64x(-1);
7117        let mask = 0b11111111;
7118        let r = _mm_mask_cmplt_epi64_mask(mask, a, b);
7119        assert_eq!(r, 0b00000001);
7120    }
7121
7122    #[simd_test(enable = "avx512f")]
7123    unsafe fn test_mm512_cmpgt_epi64_mask() {
7124        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7125        let b = _mm512_set1_epi64(-1);
7126        let m = _mm512_cmpgt_epi64_mask(b, a);
7127        assert_eq!(m, 0b00000101);
7128    }
7129
7130    #[simd_test(enable = "avx512f")]
7131    unsafe fn test_mm512_mask_cmpgt_epi64_mask() {
7132        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7133        let b = _mm512_set1_epi64(-1);
7134        let mask = 0b01100110;
7135        let r = _mm512_mask_cmpgt_epi64_mask(mask, b, a);
7136        assert_eq!(r, 0b00000100);
7137    }
7138
7139    #[simd_test(enable = "avx512f,avx512vl")]
7140    unsafe fn test_mm256_cmpgt_epi64_mask() {
7141        let a = _mm256_set_epi64x(0, 1, -1, 13);
7142        let b = _mm256_set1_epi64x(-1);
7143        let r = _mm256_cmpgt_epi64_mask(a, b);
7144        assert_eq!(r, 0b00001101);
7145    }
7146
7147    #[simd_test(enable = "avx512f,avx512vl")]
7148    unsafe fn test_mm256_mask_cmpgt_epi64_mask() {
7149        let a = _mm256_set_epi64x(0, 1, -1, 13);
7150        let b = _mm256_set1_epi64x(-1);
7151        let mask = 0b11111111;
7152        let r = _mm256_mask_cmpgt_epi64_mask(mask, a, b);
7153        assert_eq!(r, 0b00001101);
7154    }
7155
7156    #[simd_test(enable = "avx512f,avx512vl")]
7157    unsafe fn test_mm_cmpgt_epi64_mask() {
7158        let a = _mm_set_epi64x(0, -1);
7159        let b = _mm_set1_epi64x(-1);
7160        let r = _mm_cmpgt_epi64_mask(a, b);
7161        assert_eq!(r, 0b00000010);
7162    }
7163
7164    #[simd_test(enable = "avx512f,avx512vl")]
7165    unsafe fn test_mm_mask_cmpgt_epi64_mask() {
7166        let a = _mm_set_epi64x(0, -1);
7167        let b = _mm_set1_epi64x(-1);
7168        let mask = 0b11111111;
7169        let r = _mm_mask_cmpgt_epi64_mask(mask, a, b);
7170        assert_eq!(r, 0b00000010);
7171    }
7172
7173    #[simd_test(enable = "avx512f")]
7174    unsafe fn test_mm512_cmple_epi64_mask() {
7175        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7176        let b = _mm512_set1_epi64(-1);
7177        assert_eq!(
7178            _mm512_cmple_epi64_mask(a, b),
7179            !_mm512_cmpgt_epi64_mask(a, b)
7180        )
7181    }
7182
7183    #[simd_test(enable = "avx512f")]
7184    unsafe fn test_mm512_mask_cmple_epi64_mask() {
7185        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7186        let b = _mm512_set1_epi64(-1);
7187        let mask = 0b01111010;
7188        assert_eq!(_mm512_mask_cmple_epi64_mask(mask, a, b), 0b00110000);
7189    }
7190
7191    #[simd_test(enable = "avx512f,avx512vl")]
7192    unsafe fn test_mm256_cmple_epi64_mask() {
7193        let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7194        let b = _mm256_set1_epi64x(-1);
7195        let r = _mm256_cmple_epi64_mask(a, b);
7196        assert_eq!(r, 0b00000010)
7197    }
7198
7199    #[simd_test(enable = "avx512f,avx512vl")]
7200    unsafe fn test_mm256_mask_cmple_epi64_mask() {
7201        let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7202        let b = _mm256_set1_epi64x(-1);
7203        let mask = 0b11111111;
7204        let r = _mm256_mask_cmple_epi64_mask(mask, a, b);
7205        assert_eq!(r, 0b00000010)
7206    }
7207
7208    #[simd_test(enable = "avx512f,avx512vl")]
7209    unsafe fn test_mm_cmple_epi64_mask() {
7210        let a = _mm_set_epi64x(0, 1);
7211        let b = _mm_set1_epi64x(1);
7212        let r = _mm_cmple_epi64_mask(a, b);
7213        assert_eq!(r, 0b00000011)
7214    }
7215
7216    #[simd_test(enable = "avx512f,avx512vl")]
7217    unsafe fn test_mm_mask_cmple_epi64_mask() {
7218        let a = _mm_set_epi64x(0, 1);
7219        let b = _mm_set1_epi64x(1);
7220        let mask = 0b11111111;
7221        let r = _mm_mask_cmple_epi64_mask(mask, a, b);
7222        assert_eq!(r, 0b00000011)
7223    }
7224
7225    #[simd_test(enable = "avx512f")]
7226    unsafe fn test_mm512_cmpge_epi64_mask() {
7227        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7228        let b = _mm512_set1_epi64(-1);
7229        assert_eq!(
7230            _mm512_cmpge_epi64_mask(a, b),
7231            !_mm512_cmplt_epi64_mask(a, b)
7232        )
7233    }
7234
7235    #[simd_test(enable = "avx512f")]
7236    unsafe fn test_mm512_mask_cmpge_epi64_mask() {
7237        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7238        let b = _mm512_set1_epi64(-1);
7239        let mask = 0b11111111;
7240        let r = _mm512_mask_cmpge_epi64_mask(mask, a, b);
7241        assert_eq!(r, 0b11111010);
7242    }
7243
7244    #[simd_test(enable = "avx512f,avx512vl")]
7245    unsafe fn test_mm256_cmpge_epi64_mask() {
7246        let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7247        let b = _mm256_set1_epi64x(-1);
7248        let r = _mm256_cmpge_epi64_mask(a, b);
7249        assert_eq!(r, 0b00001111);
7250    }
7251
7252    #[simd_test(enable = "avx512f,avx512vl")]
7253    unsafe fn test_mm256_mask_cmpge_epi64_mask() {
7254        let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7255        let b = _mm256_set1_epi64x(-1);
7256        let mask = 0b11111111;
7257        let r = _mm256_mask_cmpge_epi64_mask(mask, a, b);
7258        assert_eq!(r, 0b00001111);
7259    }
7260
7261    #[simd_test(enable = "avx512f,avx512vl")]
7262    unsafe fn test_mm_cmpge_epi64_mask() {
7263        let a = _mm_set_epi64x(0, 1);
7264        let b = _mm_set1_epi64x(-1);
7265        let r = _mm_cmpge_epi64_mask(a, b);
7266        assert_eq!(r, 0b00000011);
7267    }
7268
7269    #[simd_test(enable = "avx512f,avx512vl")]
7270    unsafe fn test_mm_mask_cmpge_epi64_mask() {
7271        let a = _mm_set_epi64x(0, 1);
7272        let b = _mm_set1_epi64x(-1);
7273        let mask = 0b11111111;
7274        let r = _mm_mask_cmpge_epi64_mask(mask, a, b);
7275        assert_eq!(r, 0b00000011);
7276    }
7277
7278    #[simd_test(enable = "avx512f")]
7279    unsafe fn test_mm512_cmpeq_epi64_mask() {
7280        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7281        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7282        let m = _mm512_cmpeq_epi64_mask(b, a);
7283        assert_eq!(m, 0b11001111);
7284    }
7285
7286    #[simd_test(enable = "avx512f")]
7287    unsafe fn test_mm512_mask_cmpeq_epi64_mask() {
7288        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7289        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7290        let mask = 0b01111010;
7291        let r = _mm512_mask_cmpeq_epi64_mask(mask, b, a);
7292        assert_eq!(r, 0b01001010);
7293    }
7294
7295    #[simd_test(enable = "avx512f,avx512vl")]
7296    unsafe fn test_mm256_cmpeq_epi64_mask() {
7297        let a = _mm256_set_epi64x(0, 1, -1, 13);
7298        let b = _mm256_set_epi64x(0, 1, 13, 42);
7299        let m = _mm256_cmpeq_epi64_mask(b, a);
7300        assert_eq!(m, 0b00001100);
7301    }
7302
7303    #[simd_test(enable = "avx512f,avx512vl")]
7304    unsafe fn test_mm256_mask_cmpeq_epi64_mask() {
7305        let a = _mm256_set_epi64x(0, 1, -1, 13);
7306        let b = _mm256_set_epi64x(0, 1, 13, 42);
7307        let mask = 0b11111111;
7308        let r = _mm256_mask_cmpeq_epi64_mask(mask, b, a);
7309        assert_eq!(r, 0b00001100);
7310    }
7311
7312    #[simd_test(enable = "avx512f,avx512vl")]
7313    unsafe fn test_mm_cmpeq_epi64_mask() {
7314        let a = _mm_set_epi64x(0, 1);
7315        let b = _mm_set_epi64x(0, 1);
7316        let m = _mm_cmpeq_epi64_mask(b, a);
7317        assert_eq!(m, 0b00000011);
7318    }
7319
7320    #[simd_test(enable = "avx512f,avx512vl")]
7321    unsafe fn test_mm_mask_cmpeq_epi64_mask() {
7322        let a = _mm_set_epi64x(0, 1);
7323        let b = _mm_set_epi64x(0, 1);
7324        let mask = 0b11111111;
7325        let r = _mm_mask_cmpeq_epi64_mask(mask, b, a);
7326        assert_eq!(r, 0b00000011);
7327    }
7328
7329    #[simd_test(enable = "avx512f")]
7330    unsafe fn test_mm512_set_epi64() {
7331        let r = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
7332        assert_eq_m512i(r, _mm512_set_epi64(7, 6, 5, 4, 3, 2, 1, 0))
7333    }
7334
7335    #[simd_test(enable = "avx512f")]
7336    unsafe fn test_mm512_setr_epi64() {
7337        let r = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
7338        assert_eq_m512i(r, _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0))
7339    }
7340
7341    #[simd_test(enable = "avx512f")]
7342    unsafe fn test_mm512_cmpneq_epi64_mask() {
7343        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7344        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7345        let m = _mm512_cmpneq_epi64_mask(b, a);
7346        assert_eq!(m, !_mm512_cmpeq_epi64_mask(b, a));
7347    }
7348
7349    #[simd_test(enable = "avx512f")]
7350    unsafe fn test_mm512_mask_cmpneq_epi64_mask() {
7351        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, -100, 100);
7352        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7353        let mask = 0b01111010;
7354        let r = _mm512_mask_cmpneq_epi64_mask(mask, b, a);
7355        assert_eq!(r, 0b00110010)
7356    }
7357
7358    #[simd_test(enable = "avx512f,avx512vl")]
7359    unsafe fn test_mm256_cmpneq_epi64_mask() {
7360        let a = _mm256_set_epi64x(0, 1, -1, 13);
7361        let b = _mm256_set_epi64x(0, 1, 13, 42);
7362        let r = _mm256_cmpneq_epi64_mask(b, a);
7363        assert_eq!(r, 0b00000011)
7364    }
7365
7366    #[simd_test(enable = "avx512f,avx512vl")]
7367    unsafe fn test_mm256_mask_cmpneq_epi64_mask() {
7368        let a = _mm256_set_epi64x(0, 1, -1, 13);
7369        let b = _mm256_set_epi64x(0, 1, 13, 42);
7370        let mask = 0b11111111;
7371        let r = _mm256_mask_cmpneq_epi64_mask(mask, b, a);
7372        assert_eq!(r, 0b00000011)
7373    }
7374
7375    #[simd_test(enable = "avx512f,avx512vl")]
7376    unsafe fn test_mm_cmpneq_epi64_mask() {
7377        let a = _mm_set_epi64x(-1, 13);
7378        let b = _mm_set_epi64x(13, 42);
7379        let r = _mm_cmpneq_epi64_mask(b, a);
7380        assert_eq!(r, 0b00000011)
7381    }
7382
7383    #[simd_test(enable = "avx512f,avx512vl")]
7384    unsafe fn test_mm_mask_cmpneq_epi64_mask() {
7385        let a = _mm_set_epi64x(-1, 13);
7386        let b = _mm_set_epi64x(13, 42);
7387        let mask = 0b11111111;
7388        let r = _mm_mask_cmpneq_epi64_mask(mask, b, a);
7389        assert_eq!(r, 0b00000011)
7390    }
7391
7392    #[simd_test(enable = "avx512f")]
7393    unsafe fn test_mm512_cmp_epi64_mask() {
7394        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7395        let b = _mm512_set1_epi64(-1);
7396        let m = _mm512_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7397        assert_eq!(m, 0b00000101);
7398    }
7399
7400    #[simd_test(enable = "avx512f")]
7401    unsafe fn test_mm512_mask_cmp_epi64_mask() {
7402        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7403        let b = _mm512_set1_epi64(-1);
7404        let mask = 0b01100110;
7405        let r = _mm512_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7406        assert_eq!(r, 0b00000100);
7407    }
7408
7409    #[simd_test(enable = "avx512f,avx512vl")]
7410    unsafe fn test_mm256_cmp_epi64_mask() {
7411        let a = _mm256_set_epi64x(0, 1, -1, 13);
7412        let b = _mm256_set1_epi64x(1);
7413        let m = _mm256_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7414        assert_eq!(m, 0b00001010);
7415    }
7416
7417    #[simd_test(enable = "avx512f,avx512vl")]
7418    unsafe fn test_mm256_mask_cmp_epi64_mask() {
7419        let a = _mm256_set_epi64x(0, 1, -1, 13);
7420        let b = _mm256_set1_epi64x(1);
7421        let mask = 0b11111111;
7422        let r = _mm256_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7423        assert_eq!(r, 0b00001010);
7424    }
7425
7426    #[simd_test(enable = "avx512f,avx512vl")]
7427    unsafe fn test_mm_cmp_epi64_mask() {
7428        let a = _mm_set_epi64x(0, 1);
7429        let b = _mm_set1_epi64x(1);
7430        let m = _mm_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7431        assert_eq!(m, 0b00000010);
7432    }
7433
7434    #[simd_test(enable = "avx512f,avx512vl")]
7435    unsafe fn test_mm_mask_cmp_epi64_mask() {
7436        let a = _mm_set_epi64x(0, 1);
7437        let b = _mm_set1_epi64x(1);
7438        let mask = 0b11111111;
7439        let r = _mm_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7440        assert_eq!(r, 0b00000010);
7441    }
7442
7443    #[simd_test(enable = "avx512f")]
7444    unsafe fn test_mm512_i32gather_pd() {
7445        let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7446        // A multiplier of 8 is word-addressing
7447        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7448        let r = _mm512_i32gather_pd::<8>(index, arr.as_ptr());
7449        assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.));
7450    }
7451
7452    #[simd_test(enable = "avx512f")]
7453    unsafe fn test_mm512_mask_i32gather_pd() {
7454        let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7455        let src = _mm512_set1_pd(2.);
7456        let mask = 0b10101010;
7457        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7458        // A multiplier of 8 is word-addressing
7459        let r = _mm512_mask_i32gather_pd::<8>(src, mask, index, arr.as_ptr());
7460        assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.));
7461    }
7462
7463    #[simd_test(enable = "avx512f")]
7464    unsafe fn test_mm512_i64gather_pd() {
7465        let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7466        // A multiplier of 8 is word-addressing
7467        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7468        let r = _mm512_i64gather_pd::<8>(index, arr.as_ptr());
7469        assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.));
7470    }
7471
7472    #[simd_test(enable = "avx512f")]
7473    unsafe fn test_mm512_mask_i64gather_pd() {
7474        let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7475        let src = _mm512_set1_pd(2.);
7476        let mask = 0b10101010;
7477        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7478        // A multiplier of 8 is word-addressing
7479        let r = _mm512_mask_i64gather_pd::<8>(src, mask, index, arr.as_ptr());
7480        assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.));
7481    }
7482
7483    #[simd_test(enable = "avx512f")]
7484    unsafe fn test_mm512_i64gather_ps() {
7485        let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
7486        // A multiplier of 4 is word-addressing
7487        #[rustfmt::skip]
7488        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7489        let r = _mm512_i64gather_ps::<4>(index, arr.as_ptr());
7490        assert_eq_m256(r, _mm256_setr_ps(0., 16., 32., 48., 64., 80., 96., 112.));
7491    }
7492
7493    #[simd_test(enable = "avx512f")]
7494    unsafe fn test_mm512_mask_i64gather_ps() {
7495        let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
7496        let src = _mm256_set1_ps(2.);
7497        let mask = 0b10101010;
7498        #[rustfmt::skip]
7499        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7500        // A multiplier of 4 is word-addressing
7501        let r = _mm512_mask_i64gather_ps::<4>(src, mask, index, arr.as_ptr());
7502        assert_eq_m256(r, _mm256_setr_ps(2., 16., 2., 48., 2., 80., 2., 112.));
7503    }
7504
7505    #[simd_test(enable = "avx512f")]
7506    unsafe fn test_mm512_i32gather_epi64() {
7507        let mut arr = [0i64; 128];
7508        for i in 0..128i64 {
7509            arr[i as usize] = i;
7510        }
7511        // A multiplier of 8 is word-addressing
7512        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7513        let r = _mm512_i32gather_epi64::<8>(index, arr.as_ptr());
7514        assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112));
7515    }
7516
7517    #[simd_test(enable = "avx512f")]
7518    unsafe fn test_mm512_mask_i32gather_epi64() {
7519        let mut arr = [0i64; 128];
7520        for i in 0..128i64 {
7521            arr[i as usize] = i;
7522        }
7523        let src = _mm512_set1_epi64(2);
7524        let mask = 0b10101010;
7525        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7526        // A multiplier of 8 is word-addressing
7527        let r = _mm512_mask_i32gather_epi64::<8>(src, mask, index, arr.as_ptr());
7528        assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112));
7529    }
7530
7531    #[simd_test(enable = "avx512f")]
7532    unsafe fn test_mm512_i64gather_epi64() {
7533        let mut arr = [0i64; 128];
7534        for i in 0..128i64 {
7535            arr[i as usize] = i;
7536        }
7537        // A multiplier of 8 is word-addressing
7538        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7539        let r = _mm512_i64gather_epi64::<8>(index, arr.as_ptr());
7540        assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112));
7541    }
7542
7543    #[simd_test(enable = "avx512f")]
7544    unsafe fn test_mm512_mask_i64gather_epi64() {
7545        let mut arr = [0i64; 128];
7546        for i in 0..128i64 {
7547            arr[i as usize] = i;
7548        }
7549        let src = _mm512_set1_epi64(2);
7550        let mask = 0b10101010;
7551        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7552        // A multiplier of 8 is word-addressing
7553        let r = _mm512_mask_i64gather_epi64::<8>(src, mask, index, arr.as_ptr());
7554        assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112));
7555    }
7556
7557    #[simd_test(enable = "avx512f")]
7558    unsafe fn test_mm512_i64gather_epi32() {
7559        let mut arr = [0i64; 128];
7560        for i in 0..128i64 {
7561            arr[i as usize] = i;
7562        }
7563        // A multiplier of 8 is word-addressing
7564        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7565        let r = _mm512_i64gather_epi32::<8>(index, arr.as_ptr() as *const i32);
7566        assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112));
7567    }
7568
7569    #[simd_test(enable = "avx512f")]
7570    unsafe fn test_mm512_mask_i64gather_epi32() {
7571        let mut arr = [0i64; 128];
7572        for i in 0..128i64 {
7573            arr[i as usize] = i;
7574        }
7575        let src = _mm256_set1_epi32(2);
7576        let mask = 0b10101010;
7577        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7578        // A multiplier of 8 is word-addressing
7579        let r = _mm512_mask_i64gather_epi32::<8>(src, mask, index, arr.as_ptr() as *const i32);
7580        assert_eq_m256i(r, _mm256_setr_epi32(2, 16, 2, 48, 2, 80, 2, 112));
7581    }
7582
7583    #[simd_test(enable = "avx512f")]
7584    unsafe fn test_mm512_i32scatter_pd() {
7585        let mut arr = [0f64; 128];
7586        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7587        let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7588        // A multiplier of 8 is word-addressing
7589        _mm512_i32scatter_pd::<8>(arr.as_mut_ptr(), index, src);
7590        let mut expected = [0f64; 128];
7591        for i in 0..8 {
7592            expected[i * 16] = (i + 1) as f64;
7593        }
7594        assert_eq!(&arr[..], &expected[..],);
7595    }
7596
7597    #[simd_test(enable = "avx512f")]
7598    unsafe fn test_mm512_mask_i32scatter_pd() {
7599        let mut arr = [0f64; 128];
7600        let mask = 0b10101010;
7601        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7602        let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7603        // A multiplier of 8 is word-addressing
7604        _mm512_mask_i32scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src);
7605        let mut expected = [0f64; 128];
7606        for i in 0..4 {
7607            expected[i * 32 + 16] = 2. * (i + 1) as f64;
7608        }
7609        assert_eq!(&arr[..], &expected[..],);
7610    }
7611
7612    #[simd_test(enable = "avx512f")]
7613    unsafe fn test_mm512_i64scatter_pd() {
7614        let mut arr = [0f64; 128];
7615        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7616        let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7617        // A multiplier of 8 is word-addressing
7618        _mm512_i64scatter_pd::<8>(arr.as_mut_ptr(), index, src);
7619        let mut expected = [0f64; 128];
7620        for i in 0..8 {
7621            expected[i * 16] = (i + 1) as f64;
7622        }
7623        assert_eq!(&arr[..], &expected[..],);
7624    }
7625
7626    #[simd_test(enable = "avx512f")]
7627    unsafe fn test_mm512_mask_i64scatter_pd() {
7628        let mut arr = [0f64; 128];
7629        let mask = 0b10101010;
7630        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7631        let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7632        // A multiplier of 8 is word-addressing
7633        _mm512_mask_i64scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src);
7634        let mut expected = [0f64; 128];
7635        for i in 0..4 {
7636            expected[i * 32 + 16] = 2. * (i + 1) as f64;
7637        }
7638        assert_eq!(&arr[..], &expected[..],);
7639    }
7640
7641    #[simd_test(enable = "avx512f")]
7642    unsafe fn test_mm512_i64scatter_ps() {
7643        let mut arr = [0f32; 128];
7644        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7645        let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
7646        // A multiplier of 4 is word-addressing
7647        _mm512_i64scatter_ps::<4>(arr.as_mut_ptr(), index, src);
7648        let mut expected = [0f32; 128];
7649        for i in 0..8 {
7650            expected[i * 16] = (i + 1) as f32;
7651        }
7652        assert_eq!(&arr[..], &expected[..],);
7653    }
7654
7655    #[simd_test(enable = "avx512f")]
7656    unsafe fn test_mm512_mask_i64scatter_ps() {
7657        let mut arr = [0f32; 128];
7658        let mask = 0b10101010;
7659        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7660        let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
7661        // A multiplier of 4 is word-addressing
7662        _mm512_mask_i64scatter_ps::<4>(arr.as_mut_ptr(), mask, index, src);
7663        let mut expected = [0f32; 128];
7664        for i in 0..4 {
7665            expected[i * 32 + 16] = 2. * (i + 1) as f32;
7666        }
7667        assert_eq!(&arr[..], &expected[..],);
7668    }
7669
7670    #[simd_test(enable = "avx512f")]
7671    unsafe fn test_mm512_i32scatter_epi64() {
7672        let mut arr = [0i64; 128];
7673        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7674        let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7675        // A multiplier of 8 is word-addressing
7676        _mm512_i32scatter_epi64::<8>(arr.as_mut_ptr(), index, src);
7677        let mut expected = [0i64; 128];
7678        for i in 0..8 {
7679            expected[i * 16] = (i + 1) as i64;
7680        }
7681        assert_eq!(&arr[..], &expected[..],);
7682    }
7683
7684    #[simd_test(enable = "avx512f")]
7685    unsafe fn test_mm512_mask_i32scatter_epi64() {
7686        let mut arr = [0i64; 128];
7687        let mask = 0b10101010;
7688        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7689        let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7690        // A multiplier of 8 is word-addressing
7691        _mm512_mask_i32scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src);
7692        let mut expected = [0i64; 128];
7693        for i in 0..4 {
7694            expected[i * 32 + 16] = 2 * (i + 1) as i64;
7695        }
7696        assert_eq!(&arr[..], &expected[..],);
7697    }
7698
7699    #[simd_test(enable = "avx512f")]
7700    unsafe fn test_mm512_i64scatter_epi64() {
7701        let mut arr = [0i64; 128];
7702        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7703        let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7704        // A multiplier of 8 is word-addressing
7705        _mm512_i64scatter_epi64::<8>(arr.as_mut_ptr(), index, src);
7706        let mut expected = [0i64; 128];
7707        for i in 0..8 {
7708            expected[i * 16] = (i + 1) as i64;
7709        }
7710        assert_eq!(&arr[..], &expected[..],);
7711    }
7712
7713    #[simd_test(enable = "avx512f")]
7714    unsafe fn test_mm512_mask_i64scatter_epi64() {
7715        let mut arr = [0i64; 128];
7716        let mask = 0b10101010;
7717        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7718        let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7719        // A multiplier of 8 is word-addressing
7720        _mm512_mask_i64scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src);
7721        let mut expected = [0i64; 128];
7722        for i in 0..4 {
7723            expected[i * 32 + 16] = 2 * (i + 1) as i64;
7724        }
7725        assert_eq!(&arr[..], &expected[..],);
7726    }
7727
7728    #[simd_test(enable = "avx512f")]
7729    unsafe fn test_mm512_i64scatter_epi32() {
7730        let mut arr = [0i32; 128];
7731        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7732        let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
7733        // A multiplier of 4 is word-addressing
7734        _mm512_i64scatter_epi32::<4>(arr.as_mut_ptr(), index, src);
7735        let mut expected = [0i32; 128];
7736        for i in 0..8 {
7737            expected[i * 16] = (i + 1) as i32;
7738        }
7739        assert_eq!(&arr[..], &expected[..],);
7740    }
7741
7742    #[simd_test(enable = "avx512f")]
7743    unsafe fn test_mm512_mask_i64scatter_epi32() {
7744        let mut arr = [0i32; 128];
7745        let mask = 0b10101010;
7746        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7747        let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
7748        // A multiplier of 4 is word-addressing
7749        _mm512_mask_i64scatter_epi32::<4>(arr.as_mut_ptr(), mask, index, src);
7750        let mut expected = [0i32; 128];
7751        for i in 0..4 {
7752            expected[i * 32 + 16] = 2 * (i + 1) as i32;
7753        }
7754        assert_eq!(&arr[..], &expected[..],);
7755    }
7756
7757    #[simd_test(enable = "avx512f")]
7758    unsafe fn test_mm512_i32logather_epi64() {
7759        let base_addr: [i64; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
7760        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7761        let r = _mm512_i32logather_epi64::<8>(vindex, base_addr.as_ptr());
7762        let expected = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
7763        assert_eq_m512i(expected, r);
7764    }
7765
7766    #[simd_test(enable = "avx512f")]
7767    unsafe fn test_mm512_mask_i32logather_epi64() {
7768        let base_addr: [i64; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
7769        let src = _mm512_setr_epi64(9, 10, 11, 12, 13, 14, 15, 16);
7770        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7771        let r = _mm512_mask_i32logather_epi64::<8>(src, 0b01010101, vindex, base_addr.as_ptr());
7772        let expected = _mm512_setr_epi64(2, 10, 4, 12, 6, 14, 8, 16);
7773        assert_eq_m512i(expected, r);
7774    }
7775
7776    #[simd_test(enable = "avx512f")]
7777    unsafe fn test_mm512_i32logather_pd() {
7778        let base_addr: [f64; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
7779        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7780        let r = _mm512_i32logather_pd::<8>(vindex, base_addr.as_ptr());
7781        let expected = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
7782        assert_eq_m512d(expected, r);
7783    }
7784
7785    #[simd_test(enable = "avx512f")]
7786    unsafe fn test_mm512_mask_i32logather_pd() {
7787        let base_addr: [f64; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
7788        let src = _mm512_setr_pd(9., 10., 11., 12., 13., 14., 15., 16.);
7789        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7790        let r = _mm512_mask_i32logather_pd::<8>(src, 0b01010101, vindex, base_addr.as_ptr());
7791        let expected = _mm512_setr_pd(2., 10., 4., 12., 6., 14., 8., 16.);
7792        assert_eq_m512d(expected, r);
7793    }
7794
7795    #[simd_test(enable = "avx512f")]
7796    unsafe fn test_mm512_i32loscatter_epi64() {
7797        let mut base_addr: [i64; 8] = [0; 8];
7798        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7799        let src = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
7800        _mm512_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
7801        let expected = [1, 2, 3, 4, 5, 6, 7, 8];
7802        assert_eq!(expected, base_addr);
7803    }
7804
7805    #[simd_test(enable = "avx512f")]
7806    unsafe fn test_mm512_mask_i32loscatter_epi64() {
7807        let mut base_addr: [i64; 8] = [0; 8];
7808        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7809        let src = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
7810        _mm512_mask_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
7811        let expected = [0, 2, 0, 4, 0, 6, 0, 8];
7812        assert_eq!(expected, base_addr);
7813    }
7814
7815    #[simd_test(enable = "avx512f")]
7816    unsafe fn test_mm512_i32loscatter_pd() {
7817        let mut base_addr: [f64; 8] = [0.; 8];
7818        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7819        let src = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
7820        _mm512_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
7821        let expected = [1., 2., 3., 4., 5., 6., 7., 8.];
7822        assert_eq!(expected, base_addr);
7823    }
7824
7825    #[simd_test(enable = "avx512f")]
7826    unsafe fn test_mm512_mask_i32loscatter_pd() {
7827        let mut base_addr: [f64; 8] = [0.; 8];
7828        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7829        let src = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
7830        _mm512_mask_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
7831        let expected = [0., 2., 0., 4., 0., 6., 0., 8.];
7832        assert_eq!(expected, base_addr);
7833    }
7834
7835    #[simd_test(enable = "avx512f,avx512vl")]
7836    unsafe fn test_mm_mmask_i32gather_epi32() {
7837        let base_addr: [i32; 4] = [1, 2, 3, 4];
7838        let src = _mm_setr_epi32(5, 6, 7, 8);
7839        let vindex = _mm_setr_epi32(1, 2, 3, 0);
7840        let r = _mm_mmask_i32gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr());
7841        let expected = _mm_setr_epi32(2, 6, 4, 8);
7842        assert_eq_m128i(expected, r);
7843    }
7844
7845    #[simd_test(enable = "avx512f,avx512vl")]
7846    unsafe fn test_mm_mmask_i32gather_epi64() {
7847        let base_addr: [i64; 2] = [1, 2];
7848        let src = _mm_setr_epi64x(5, 6);
7849        let vindex = _mm_setr_epi32(1, 0, -1, -1);
7850        let r = _mm_mmask_i32gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr());
7851        let expected = _mm_setr_epi64x(2, 6);
7852        assert_eq_m128i(expected, r);
7853    }
7854
7855    #[simd_test(enable = "avx512f,avx512vl")]
7856    unsafe fn test_mm_mmask_i32gather_pd() {
7857        let base_addr: [f64; 2] = [1., 2.];
7858        let src = _mm_setr_pd(5., 6.);
7859        let vindex = _mm_setr_epi32(1, 0, -1, -1);
7860        let r = _mm_mmask_i32gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr());
7861        let expected = _mm_setr_pd(2., 6.);
7862        assert_eq_m128d(expected, r);
7863    }
7864
7865    #[simd_test(enable = "avx512f,avx512vl")]
7866    unsafe fn test_mm_mmask_i32gather_ps() {
7867        let base_addr: [f32; 4] = [1., 2., 3., 4.];
7868        let src = _mm_setr_ps(5., 6., 7., 8.);
7869        let vindex = _mm_setr_epi32(1, 2, 3, 0);
7870        let r = _mm_mmask_i32gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr());
7871        let expected = _mm_setr_ps(2., 6., 4., 8.);
7872        assert_eq_m128(expected, r);
7873    }
7874
7875    #[simd_test(enable = "avx512f,avx512vl")]
7876    unsafe fn test_mm_mmask_i64gather_epi32() {
7877        let base_addr: [i32; 2] = [1, 2];
7878        let src = _mm_setr_epi32(5, 6, 7, 8);
7879        let vindex = _mm_setr_epi64x(1, 0);
7880        let r = _mm_mmask_i64gather_epi32::<4>(src, 0b01, vindex, base_addr.as_ptr());
7881        let expected = _mm_setr_epi32(2, 6, 0, 0);
7882        assert_eq_m128i(expected, r);
7883    }
7884
7885    #[simd_test(enable = "avx512f,avx512vl")]
7886    unsafe fn test_mm_mmask_i64gather_epi64() {
7887        let base_addr: [i64; 2] = [1, 2];
7888        let src = _mm_setr_epi64x(5, 6);
7889        let vindex = _mm_setr_epi64x(1, 0);
7890        let r = _mm_mmask_i64gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr());
7891        let expected = _mm_setr_epi64x(2, 6);
7892        assert_eq_m128i(expected, r);
7893    }
7894
7895    #[simd_test(enable = "avx512f,avx512vl")]
7896    unsafe fn test_mm_mmask_i64gather_pd() {
7897        let base_addr: [f64; 2] = [1., 2.];
7898        let src = _mm_setr_pd(5., 6.);
7899        let vindex = _mm_setr_epi64x(1, 0);
7900        let r = _mm_mmask_i64gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr());
7901        let expected = _mm_setr_pd(2., 6.);
7902        assert_eq_m128d(expected, r);
7903    }
7904
7905    #[simd_test(enable = "avx512f,avx512vl")]
7906    unsafe fn test_mm_mmask_i64gather_ps() {
7907        let base_addr: [f32; 2] = [1., 2.];
7908        let src = _mm_setr_ps(5., 6., 7., 8.);
7909        let vindex = _mm_setr_epi64x(1, 0);
7910        let r = _mm_mmask_i64gather_ps::<4>(src, 0b01, vindex, base_addr.as_ptr());
7911        let expected = _mm_setr_ps(2., 6., 0., 0.);
7912        assert_eq_m128(expected, r);
7913    }
7914
7915    #[simd_test(enable = "avx512f,avx512vl")]
7916    unsafe fn test_mm256_mmask_i32gather_epi32() {
7917        let base_addr: [i32; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
7918        let src = _mm256_setr_epi32(9, 10, 11, 12, 13, 14, 15, 16);
7919        let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
7920        let r = _mm256_mmask_i32gather_epi32::<4>(src, 0b01010101, vindex, base_addr.as_ptr());
7921        let expected = _mm256_setr_epi32(2, 10, 4, 12, 6, 14, 8, 16);
7922        assert_eq_m256i(expected, r);
7923    }
7924
7925    #[simd_test(enable = "avx512f,avx512vl")]
7926    unsafe fn test_mm256_mmask_i32gather_epi64() {
7927        let base_addr: [i64; 4] = [1, 2, 3, 4];
7928        let src = _mm256_setr_epi64x(9, 10, 11, 12);
7929        let vindex = _mm_setr_epi32(1, 2, 3, 4);
7930        let r = _mm256_mmask_i32gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr());
7931        let expected = _mm256_setr_epi64x(2, 10, 4, 12);
7932        assert_eq_m256i(expected, r);
7933    }
7934
7935    #[simd_test(enable = "avx512f,avx512vl")]
7936    unsafe fn test_mm256_mmask_i32gather_pd() {
7937        let base_addr: [f64; 4] = [1., 2., 3., 4.];
7938        let src = _mm256_setr_pd(9., 10., 11., 12.);
7939        let vindex = _mm_setr_epi32(1, 2, 3, 4);
7940        let r = _mm256_mmask_i32gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr());
7941        let expected = _mm256_setr_pd(2., 10., 4., 12.);
7942        assert_eq_m256d(expected, r);
7943    }
7944
7945    #[simd_test(enable = "avx512f,avx512vl")]
7946    unsafe fn test_mm256_mmask_i32gather_ps() {
7947        let base_addr: [f32; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
7948        let src = _mm256_setr_ps(9., 10., 11., 12., 13., 14., 15., 16.);
7949        let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
7950        let r = _mm256_mmask_i32gather_ps::<4>(src, 0b01010101, vindex, base_addr.as_ptr());
7951        let expected = _mm256_setr_ps(2., 10., 4., 12., 6., 14., 8., 16.);
7952        assert_eq_m256(expected, r);
7953    }
7954
7955    #[simd_test(enable = "avx512f,avx512vl")]
7956    unsafe fn test_mm256_mmask_i64gather_epi32() {
7957        let base_addr: [i32; 4] = [1, 2, 3, 4];
7958        let src = _mm_setr_epi32(9, 10, 11, 12);
7959        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
7960        let r = _mm256_mmask_i64gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr());
7961        let expected = _mm_setr_epi32(2, 10, 4, 12);
7962        assert_eq_m128i(expected, r);
7963    }
7964
7965    #[simd_test(enable = "avx512f,avx512vl")]
7966    unsafe fn test_mm256_mmask_i64gather_epi64() {
7967        let base_addr: [i64; 4] = [1, 2, 3, 4];
7968        let src = _mm256_setr_epi64x(9, 10, 11, 12);
7969        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
7970        let r = _mm256_mmask_i64gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr());
7971        let expected = _mm256_setr_epi64x(2, 10, 4, 12);
7972        assert_eq_m256i(expected, r);
7973    }
7974
7975    #[simd_test(enable = "avx512f,avx512vl")]
7976    unsafe fn test_mm256_mmask_i64gather_pd() {
7977        let base_addr: [f64; 4] = [1., 2., 3., 4.];
7978        let src = _mm256_setr_pd(9., 10., 11., 12.);
7979        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
7980        let r = _mm256_mmask_i64gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr());
7981        let expected = _mm256_setr_pd(2., 10., 4., 12.);
7982        assert_eq_m256d(expected, r);
7983    }
7984
7985    #[simd_test(enable = "avx512f,avx512vl")]
7986    unsafe fn test_mm256_mmask_i64gather_ps() {
7987        let base_addr: [f32; 4] = [1., 2., 3., 4.];
7988        let src = _mm_setr_ps(9., 10., 11., 12.);
7989        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
7990        let r = _mm256_mmask_i64gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr());
7991        let expected = _mm_setr_ps(2., 10., 4., 12.);
7992        assert_eq_m128(expected, r);
7993    }
7994
7995    #[simd_test(enable = "avx512f,avx512vl")]
7996    unsafe fn test_mm_i32scatter_epi32() {
7997        let mut base_addr: [i32; 4] = [0; 4];
7998        let vindex = _mm_setr_epi32(1, 2, 3, 0);
7999        let src = _mm_setr_epi32(2, 3, 4, 1);
8000        _mm_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
8001        let expected = [1, 2, 3, 4];
8002        assert_eq!(expected, base_addr);
8003    }
8004
8005    #[simd_test(enable = "avx512f,avx512vl")]
8006    unsafe fn test_mm_mask_i32scatter_epi32() {
8007        let mut base_addr: [i32; 4] = [0; 4];
8008        let vindex = _mm_setr_epi32(1, 2, 3, 0);
8009        let src = _mm_setr_epi32(2, 3, 4, 1);
8010        _mm_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8011        let expected = [0, 2, 0, 4];
8012        assert_eq!(expected, base_addr);
8013    }
8014
8015    #[simd_test(enable = "avx512f,avx512vl")]
8016    unsafe fn test_mm_i32scatter_epi64() {
8017        let mut base_addr: [i64; 2] = [0; 2];
8018        let vindex = _mm_setr_epi32(1, 0, -1, -1);
8019        let src = _mm_setr_epi64x(2, 1);
8020        _mm_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
8021        let expected = [1, 2];
8022        assert_eq!(expected, base_addr);
8023    }
8024
8025    #[simd_test(enable = "avx512f,avx512vl")]
8026    unsafe fn test_mm_mask_i32scatter_epi64() {
8027        let mut base_addr: [i64; 2] = [0; 2];
8028        let vindex = _mm_setr_epi32(1, 0, -1, -1);
8029        let src = _mm_setr_epi64x(2, 1);
8030        _mm_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8031        let expected = [0, 2];
8032        assert_eq!(expected, base_addr);
8033    }
8034
8035    #[simd_test(enable = "avx512f,avx512vl")]
8036    unsafe fn test_mm_i32scatter_pd() {
8037        let mut base_addr: [f64; 2] = [0.; 2];
8038        let vindex = _mm_setr_epi32(1, 0, -1, -1);
8039        let src = _mm_setr_pd(2., 1.);
8040        _mm_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
8041        let expected = [1., 2.];
8042        assert_eq!(expected, base_addr);
8043    }
8044
8045    #[simd_test(enable = "avx512f,avx512vl")]
8046    unsafe fn test_mm_mask_i32scatter_pd() {
8047        let mut base_addr: [f64; 2] = [0.; 2];
8048        let vindex = _mm_setr_epi32(1, 0, -1, -1);
8049        let src = _mm_setr_pd(2., 1.);
8050        _mm_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8051        let expected = [0., 2.];
8052        assert_eq!(expected, base_addr);
8053    }
8054
8055    #[simd_test(enable = "avx512f,avx512vl")]
8056    unsafe fn test_mm_i32scatter_ps() {
8057        let mut base_addr: [f32; 4] = [0.; 4];
8058        let vindex = _mm_setr_epi32(1, 2, 3, 0);
8059        let src = _mm_setr_ps(2., 3., 4., 1.);
8060        _mm_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
8061        let expected = [1., 2., 3., 4.];
8062        assert_eq!(expected, base_addr);
8063    }
8064
8065    #[simd_test(enable = "avx512f,avx512vl")]
8066    unsafe fn test_mm_mask_i32scatter_ps() {
8067        let mut base_addr: [f32; 4] = [0.; 4];
8068        let vindex = _mm_setr_epi32(1, 2, 3, 0);
8069        let src = _mm_setr_ps(2., 3., 4., 1.);
8070        _mm_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8071        let expected = [0., 2., 0., 4.];
8072        assert_eq!(expected, base_addr);
8073    }
8074
8075    #[simd_test(enable = "avx512f,avx512vl")]
8076    unsafe fn test_mm_i64scatter_epi32() {
8077        let mut base_addr: [i32; 2] = [0; 2];
8078        let vindex = _mm_setr_epi64x(1, 0);
8079        let src = _mm_setr_epi32(2, 1, -1, -1);
8080        _mm_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
8081        let expected = [1, 2];
8082        assert_eq!(expected, base_addr);
8083    }
8084
8085    #[simd_test(enable = "avx512f,avx512vl")]
8086    unsafe fn test_mm_mask_i64scatter_epi32() {
8087        let mut base_addr: [i32; 2] = [0; 2];
8088        let vindex = _mm_setr_epi64x(1, 0);
8089        let src = _mm_setr_epi32(2, 1, -1, -1);
8090        _mm_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8091        let expected = [0, 2];
8092        assert_eq!(expected, base_addr);
8093    }
8094
8095    #[simd_test(enable = "avx512f,avx512vl")]
8096    unsafe fn test_mm_i64scatter_epi64() {
8097        let mut base_addr: [i64; 2] = [0; 2];
8098        let vindex = _mm_setr_epi64x(1, 0);
8099        let src = _mm_setr_epi64x(2, 1);
8100        _mm_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
8101        let expected = [1, 2];
8102        assert_eq!(expected, base_addr);
8103    }
8104
8105    #[simd_test(enable = "avx512f,avx512vl")]
8106    unsafe fn test_mm_mask_i64scatter_epi64() {
8107        let mut base_addr: [i64; 2] = [0; 2];
8108        let vindex = _mm_setr_epi64x(1, 0);
8109        let src = _mm_setr_epi64x(2, 1);
8110        _mm_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8111        let expected = [0, 2];
8112        assert_eq!(expected, base_addr);
8113    }
8114
8115    #[simd_test(enable = "avx512f,avx512vl")]
8116    unsafe fn test_mm_i64scatter_pd() {
8117        let mut base_addr: [f64; 2] = [0.; 2];
8118        let vindex = _mm_setr_epi64x(1, 0);
8119        let src = _mm_setr_pd(2., 1.);
8120        _mm_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
8121        let expected = [1., 2.];
8122        assert_eq!(expected, base_addr);
8123    }
8124
8125    #[simd_test(enable = "avx512f,avx512vl")]
8126    unsafe fn test_mm_mask_i64scatter_pd() {
8127        let mut base_addr: [f64; 2] = [0.; 2];
8128        let vindex = _mm_setr_epi64x(1, 0);
8129        let src = _mm_setr_pd(2., 1.);
8130        _mm_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8131        let expected = [0., 2.];
8132        assert_eq!(expected, base_addr);
8133    }
8134
8135    #[simd_test(enable = "avx512f,avx512vl")]
8136    unsafe fn test_mm_i64scatter_ps() {
8137        let mut base_addr: [f32; 2] = [0.; 2];
8138        let vindex = _mm_setr_epi64x(1, 0);
8139        let src = _mm_setr_ps(2., 1., -1., -1.);
8140        _mm_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
8141        let expected = [1., 2.];
8142        assert_eq!(expected, base_addr);
8143    }
8144
8145    #[simd_test(enable = "avx512f,avx512vl")]
8146    unsafe fn test_mm_mask_i64scatter_ps() {
8147        let mut base_addr: [f32; 2] = [0.; 2];
8148        let vindex = _mm_setr_epi64x(1, 0);
8149        let src = _mm_setr_ps(2., 1., -1., -1.);
8150        _mm_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8151        let expected = [0., 2.];
8152        assert_eq!(expected, base_addr);
8153    }
8154
8155    #[simd_test(enable = "avx512f,avx512vl")]
8156    unsafe fn test_mm256_i32scatter_epi32() {
8157        let mut base_addr: [i32; 8] = [0; 8];
8158        let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8159        let src = _mm256_setr_epi32(2, 3, 4, 5, 6, 7, 8, 1);
8160        _mm256_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
8161        let expected = [1, 2, 3, 4, 5, 6, 7, 8];
8162        assert_eq!(expected, base_addr);
8163    }
8164
8165    #[simd_test(enable = "avx512f,avx512vl")]
8166    unsafe fn test_mm256_mask_i32scatter_epi32() {
8167        let mut base_addr: [i32; 8] = [0; 8];
8168        let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8169        let src = _mm256_setr_epi32(2, 3, 4, 5, 6, 7, 8, 1);
8170        _mm256_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
8171        let expected = [0, 2, 0, 4, 0, 6, 0, 8];
8172        assert_eq!(expected, base_addr);
8173    }
8174
8175    #[simd_test(enable = "avx512f,avx512vl")]
8176    unsafe fn test_mm256_i32scatter_epi64() {
8177        let mut base_addr: [i64; 4] = [0; 4];
8178        let vindex = _mm_setr_epi32(1, 2, 3, 0);
8179        let src = _mm256_setr_epi64x(2, 3, 4, 1);
8180        _mm256_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
8181        let expected = [1, 2, 3, 4];
8182        assert_eq!(expected, base_addr);
8183    }
8184
8185    #[simd_test(enable = "avx512f,avx512vl")]
8186    unsafe fn test_mm256_mask_i32scatter_epi64() {
8187        let mut base_addr: [i64; 4] = [0; 4];
8188        let vindex = _mm_setr_epi32(1, 2, 3, 0);
8189        let src = _mm256_setr_epi64x(2, 3, 4, 1);
8190        _mm256_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8191        let expected = [0, 2, 0, 4];
8192        assert_eq!(expected, base_addr);
8193    }
8194
8195    #[simd_test(enable = "avx512f,avx512vl")]
8196    unsafe fn test_mm256_i32scatter_pd() {
8197        let mut base_addr: [f64; 4] = [0.; 4];
8198        let vindex = _mm_setr_epi32(1, 2, 3, 0);
8199        let src = _mm256_setr_pd(2., 3., 4., 1.);
8200        _mm256_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
8201        let expected = [1., 2., 3., 4.];
8202        assert_eq!(expected, base_addr);
8203    }
8204
8205    #[simd_test(enable = "avx512f,avx512vl")]
8206    unsafe fn test_mm256_mask_i32scatter_pd() {
8207        let mut base_addr: [f64; 4] = [0.; 4];
8208        let vindex = _mm_setr_epi32(1, 2, 3, 0);
8209        let src = _mm256_setr_pd(2., 3., 4., 1.);
8210        _mm256_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8211        let expected = [0., 2., 0., 4.];
8212        assert_eq!(expected, base_addr);
8213    }
8214
8215    #[simd_test(enable = "avx512f,avx512vl")]
8216    unsafe fn test_mm256_i32scatter_ps() {
8217        let mut base_addr: [f32; 8] = [0.; 8];
8218        let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8219        let src = _mm256_setr_ps(2., 3., 4., 5., 6., 7., 8., 1.);
8220        _mm256_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
8221        let expected = [1., 2., 3., 4., 5., 6., 7., 8.];
8222        assert_eq!(expected, base_addr);
8223    }
8224
8225    #[simd_test(enable = "avx512f,avx512vl")]
8226    unsafe fn test_mm256_mask_i32scatter_ps() {
8227        let mut base_addr: [f32; 8] = [0.; 8];
8228        let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8229        let src = _mm256_setr_ps(2., 3., 4., 5., 6., 7., 8., 1.);
8230        _mm256_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
8231        let expected = [0., 2., 0., 4., 0., 6., 0., 8.];
8232        assert_eq!(expected, base_addr);
8233    }
8234
8235    #[simd_test(enable = "avx512f,avx512vl")]
8236    unsafe fn test_mm256_i64scatter_epi32() {
8237        let mut base_addr: [i32; 4] = [0; 4];
8238        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8239        let src = _mm_setr_epi32(2, 3, 4, 1);
8240        _mm256_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
8241        let expected = [1, 2, 3, 4];
8242        assert_eq!(expected, base_addr);
8243    }
8244
8245    #[simd_test(enable = "avx512f,avx512vl")]
8246    unsafe fn test_mm256_mask_i64scatter_epi32() {
8247        let mut base_addr: [i32; 4] = [0; 4];
8248        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8249        let src = _mm_setr_epi32(2, 3, 4, 1);
8250        _mm256_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8251        let expected = [0, 2, 0, 4];
8252        assert_eq!(expected, base_addr);
8253    }
8254
8255    #[simd_test(enable = "avx512f,avx512vl")]
8256    unsafe fn test_mm256_i64scatter_epi64() {
8257        let mut base_addr: [i64; 4] = [0; 4];
8258        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8259        let src = _mm256_setr_epi64x(2, 3, 4, 1);
8260        _mm256_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
8261        let expected = [1, 2, 3, 4];
8262        assert_eq!(expected, base_addr);
8263    }
8264
8265    #[simd_test(enable = "avx512f,avx512vl")]
8266    unsafe fn test_mm256_mask_i64scatter_epi64() {
8267        let mut base_addr: [i64; 4] = [0; 4];
8268        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8269        let src = _mm256_setr_epi64x(2, 3, 4, 1);
8270        _mm256_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8271        let expected = [0, 2, 0, 4];
8272        assert_eq!(expected, base_addr);
8273    }
8274
8275    #[simd_test(enable = "avx512f,avx512vl")]
8276    unsafe fn test_mm256_i64scatter_pd() {
8277        let mut base_addr: [f64; 4] = [0.; 4];
8278        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8279        let src = _mm256_setr_pd(2., 3., 4., 1.);
8280        _mm256_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
8281        let expected = [1., 2., 3., 4.];
8282        assert_eq!(expected, base_addr);
8283    }
8284
8285    #[simd_test(enable = "avx512f,avx512vl")]
8286    unsafe fn test_mm256_mask_i64scatter_pd() {
8287        let mut base_addr: [f64; 4] = [0.; 4];
8288        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8289        let src = _mm256_setr_pd(2., 3., 4., 1.);
8290        _mm256_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8291        let expected = [0., 2., 0., 4.];
8292        assert_eq!(expected, base_addr);
8293    }
8294
8295    #[simd_test(enable = "avx512f,avx512vl")]
8296    unsafe fn test_mm256_i64scatter_ps() {
8297        let mut base_addr: [f32; 4] = [0.; 4];
8298        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8299        let src = _mm_setr_ps(2., 3., 4., 1.);
8300        _mm256_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
8301        let expected = [1., 2., 3., 4.];
8302        assert_eq!(expected, base_addr);
8303    }
8304
8305    #[simd_test(enable = "avx512f,avx512vl")]
8306    unsafe fn test_mm256_mask_i64scatter_ps() {
8307        let mut base_addr: [f32; 4] = [0.; 4];
8308        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8309        let src = _mm_setr_ps(2., 3., 4., 1.);
8310        _mm256_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8311        let expected = [0., 2., 0., 4.];
8312        assert_eq!(expected, base_addr);
8313    }
8314
8315    #[simd_test(enable = "avx512f")]
8316    unsafe fn test_mm512_rol_epi64() {
8317        #[rustfmt::skip]
8318        let a = _mm512_set_epi64(
8319            1 << 63, 1 << 32, 1 << 32, 1 << 32,
8320            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8321        );
8322        let r = _mm512_rol_epi64::<1>(a);
8323        #[rustfmt::skip]
8324        let e = _mm512_set_epi64(
8325            1 << 0, 1 << 33, 1 << 33, 1 << 33,
8326            1 << 33, 1 << 33, 1 << 33, 1 << 33,
8327        );
8328        assert_eq_m512i(r, e);
8329    }
8330
8331    #[simd_test(enable = "avx512f")]
8332    unsafe fn test_mm512_mask_rol_epi64() {
8333        #[rustfmt::skip]
8334        let a = _mm512_set_epi64(
8335            1 << 63, 1 << 32, 1 << 32, 1 << 32,
8336            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8337        );
8338        let r = _mm512_mask_rol_epi64::<1>(a, 0, a);
8339        assert_eq_m512i(r, a);
8340        let r = _mm512_mask_rol_epi64::<1>(a, 0b11111111, a);
8341        #[rustfmt::skip]
8342        let e = _mm512_set_epi64(
8343            1 << 0,  1 << 33, 1 << 33, 1 << 33,
8344            1 << 33, 1 << 33, 1 << 33, 1 << 33,
8345        );
8346        assert_eq_m512i(r, e);
8347    }
8348
8349    #[simd_test(enable = "avx512f")]
8350    unsafe fn test_mm512_maskz_rol_epi64() {
8351        #[rustfmt::skip]
8352        let a = _mm512_set_epi64(
8353            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8354            1 << 32, 1 << 32, 1 << 32, 1 << 63,
8355        );
8356        let r = _mm512_maskz_rol_epi64::<1>(0, a);
8357        assert_eq_m512i(r, _mm512_setzero_si512());
8358        let r = _mm512_maskz_rol_epi64::<1>(0b00001111, a);
8359        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 1 << 0);
8360        assert_eq_m512i(r, e);
8361    }
8362
8363    #[simd_test(enable = "avx512f,avx512vl")]
8364    unsafe fn test_mm256_rol_epi64() {
8365        let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8366        let r = _mm256_rol_epi64::<1>(a);
8367        let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
8368        assert_eq_m256i(r, e);
8369    }
8370
8371    #[simd_test(enable = "avx512f,avx512vl")]
8372    unsafe fn test_mm256_mask_rol_epi64() {
8373        let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8374        let r = _mm256_mask_rol_epi64::<1>(a, 0, a);
8375        assert_eq_m256i(r, a);
8376        let r = _mm256_mask_rol_epi64::<1>(a, 0b00001111, a);
8377        let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
8378        assert_eq_m256i(r, e);
8379    }
8380
8381    #[simd_test(enable = "avx512f,avx512vl")]
8382    unsafe fn test_mm256_maskz_rol_epi64() {
8383        let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8384        let r = _mm256_maskz_rol_epi64::<1>(0, a);
8385        assert_eq_m256i(r, _mm256_setzero_si256());
8386        let r = _mm256_maskz_rol_epi64::<1>(0b00001111, a);
8387        let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
8388        assert_eq_m256i(r, e);
8389    }
8390
8391    #[simd_test(enable = "avx512f,avx512vl")]
8392    unsafe fn test_mm_rol_epi64() {
8393        let a = _mm_set_epi64x(1 << 63, 1 << 32);
8394        let r = _mm_rol_epi64::<1>(a);
8395        let e = _mm_set_epi64x(1 << 0, 1 << 33);
8396        assert_eq_m128i(r, e);
8397    }
8398
8399    #[simd_test(enable = "avx512f,avx512vl")]
8400    unsafe fn test_mm_mask_rol_epi64() {
8401        let a = _mm_set_epi64x(1 << 63, 1 << 32);
8402        let r = _mm_mask_rol_epi64::<1>(a, 0, a);
8403        assert_eq_m128i(r, a);
8404        let r = _mm_mask_rol_epi64::<1>(a, 0b00000011, a);
8405        let e = _mm_set_epi64x(1 << 0, 1 << 33);
8406        assert_eq_m128i(r, e);
8407    }
8408
8409    #[simd_test(enable = "avx512f,avx512vl")]
8410    unsafe fn test_mm_maskz_rol_epi64() {
8411        let a = _mm_set_epi64x(1 << 63, 1 << 32);
8412        let r = _mm_maskz_rol_epi64::<1>(0, a);
8413        assert_eq_m128i(r, _mm_setzero_si128());
8414        let r = _mm_maskz_rol_epi64::<1>(0b00000011, a);
8415        let e = _mm_set_epi64x(1 << 0, 1 << 33);
8416        assert_eq_m128i(r, e);
8417    }
8418
8419    #[simd_test(enable = "avx512f")]
8420    unsafe fn test_mm512_ror_epi64() {
8421        #[rustfmt::skip]
8422        let a = _mm512_set_epi64(
8423            1 << 0,  1 << 32, 1 << 32, 1 << 32,
8424            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8425        );
8426        let r = _mm512_ror_epi64::<1>(a);
8427        #[rustfmt::skip]
8428        let e = _mm512_set_epi64(
8429            1 << 63, 1 << 31, 1 << 31, 1 << 31,
8430            1 << 31, 1 << 31, 1 << 31, 1 << 31,
8431        );
8432        assert_eq_m512i(r, e);
8433    }
8434
8435    #[simd_test(enable = "avx512f")]
8436    unsafe fn test_mm512_mask_ror_epi64() {
8437        #[rustfmt::skip]
8438        let a = _mm512_set_epi64(
8439            1 << 0,  1 << 32, 1 << 32, 1 << 32,
8440            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8441        );
8442        let r = _mm512_mask_ror_epi64::<1>(a, 0, a);
8443        assert_eq_m512i(r, a);
8444        let r = _mm512_mask_ror_epi64::<1>(a, 0b11111111, a);
8445        #[rustfmt::skip]
8446        let e = _mm512_set_epi64(
8447            1 << 63, 1 << 31, 1 << 31, 1 << 31,
8448            1 << 31, 1 << 31, 1 << 31, 1 << 31,
8449        );
8450        assert_eq_m512i(r, e);
8451    }
8452
8453    #[simd_test(enable = "avx512f")]
8454    unsafe fn test_mm512_maskz_ror_epi64() {
8455        #[rustfmt::skip]
8456        let a = _mm512_set_epi64(
8457            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8458            1 << 32, 1 << 32, 1 << 32, 1 << 0,
8459        );
8460        let r = _mm512_maskz_ror_epi64::<1>(0, a);
8461        assert_eq_m512i(r, _mm512_setzero_si512());
8462        let r = _mm512_maskz_ror_epi64::<1>(0b00001111, a);
8463        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 1 << 63);
8464        assert_eq_m512i(r, e);
8465    }
8466
8467    #[simd_test(enable = "avx512f,avx512vl")]
8468    unsafe fn test_mm256_ror_epi64() {
8469        let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
8470        let r = _mm256_ror_epi64::<1>(a);
8471        let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
8472        assert_eq_m256i(r, e);
8473    }
8474
8475    #[simd_test(enable = "avx512f,avx512vl")]
8476    unsafe fn test_mm256_mask_ror_epi64() {
8477        let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
8478        let r = _mm256_mask_ror_epi64::<1>(a, 0, a);
8479        assert_eq_m256i(r, a);
8480        let r = _mm256_mask_ror_epi64::<1>(a, 0b00001111, a);
8481        let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
8482        assert_eq_m256i(r, e);
8483    }
8484
8485    #[simd_test(enable = "avx512f,avx512vl")]
8486    unsafe fn test_mm256_maskz_ror_epi64() {
8487        let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
8488        let r = _mm256_maskz_ror_epi64::<1>(0, a);
8489        assert_eq_m256i(r, _mm256_setzero_si256());
8490        let r = _mm256_maskz_ror_epi64::<1>(0b00001111, a);
8491        let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
8492        assert_eq_m256i(r, e);
8493    }
8494
8495    #[simd_test(enable = "avx512f,avx512vl")]
8496    unsafe fn test_mm_ror_epi64() {
8497        let a = _mm_set_epi64x(1 << 0, 1 << 32);
8498        let r = _mm_ror_epi64::<1>(a);
8499        let e = _mm_set_epi64x(1 << 63, 1 << 31);
8500        assert_eq_m128i(r, e);
8501    }
8502
8503    #[simd_test(enable = "avx512f,avx512vl")]
8504    unsafe fn test_mm_mask_ror_epi64() {
8505        let a = _mm_set_epi64x(1 << 0, 1 << 32);
8506        let r = _mm_mask_ror_epi64::<1>(a, 0, a);
8507        assert_eq_m128i(r, a);
8508        let r = _mm_mask_ror_epi64::<1>(a, 0b00000011, a);
8509        let e = _mm_set_epi64x(1 << 63, 1 << 31);
8510        assert_eq_m128i(r, e);
8511    }
8512
8513    #[simd_test(enable = "avx512f,avx512vl")]
8514    unsafe fn test_mm_maskz_ror_epi64() {
8515        let a = _mm_set_epi64x(1 << 0, 1 << 32);
8516        let r = _mm_maskz_ror_epi64::<1>(0, a);
8517        assert_eq_m128i(r, _mm_setzero_si128());
8518        let r = _mm_maskz_ror_epi64::<1>(0b00000011, a);
8519        let e = _mm_set_epi64x(1 << 63, 1 << 31);
8520        assert_eq_m128i(r, e);
8521    }
8522
8523    #[simd_test(enable = "avx512f")]
8524    unsafe fn test_mm512_slli_epi64() {
8525        #[rustfmt::skip]
8526        let a = _mm512_set_epi64(
8527            1 << 63, 1 << 32, 1 << 32, 1 << 32,
8528            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8529        );
8530        let r = _mm512_slli_epi64::<1>(a);
8531        #[rustfmt::skip]
8532        let e = _mm512_set_epi64(
8533            0, 1 << 33, 1 << 33, 1 << 33,
8534            1 << 33, 1 << 33, 1 << 33, 1 << 33,
8535        );
8536        assert_eq_m512i(r, e);
8537    }
8538
8539    #[simd_test(enable = "avx512f")]
8540    unsafe fn test_mm512_mask_slli_epi64() {
8541        #[rustfmt::skip]
8542        let a = _mm512_set_epi64(
8543            1 << 63, 1 << 32, 1 << 32, 1 << 32,
8544            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8545        );
8546        let r = _mm512_mask_slli_epi64::<1>(a, 0, a);
8547        assert_eq_m512i(r, a);
8548        let r = _mm512_mask_slli_epi64::<1>(a, 0b11111111, a);
8549        #[rustfmt::skip]
8550        let e = _mm512_set_epi64(
8551            0, 1 << 33, 1 << 33, 1 << 33,
8552            1 << 33, 1 << 33, 1 << 33, 1 << 33,
8553        );
8554        assert_eq_m512i(r, e);
8555    }
8556
8557    #[simd_test(enable = "avx512f")]
8558    unsafe fn test_mm512_maskz_slli_epi64() {
8559        #[rustfmt::skip]
8560        let a = _mm512_set_epi64(
8561            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8562            1 << 32, 1 << 32, 1 << 32, 1 << 63,
8563        );
8564        let r = _mm512_maskz_slli_epi64::<1>(0, a);
8565        assert_eq_m512i(r, _mm512_setzero_si512());
8566        let r = _mm512_maskz_slli_epi64::<1>(0b00001111, a);
8567        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 0);
8568        assert_eq_m512i(r, e);
8569    }
8570
8571    #[simd_test(enable = "avx512f,avx512vl")]
8572    unsafe fn test_mm256_mask_slli_epi64() {
8573        let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8574        let r = _mm256_mask_slli_epi64::<1>(a, 0, a);
8575        assert_eq_m256i(r, a);
8576        let r = _mm256_mask_slli_epi64::<1>(a, 0b00001111, a);
8577        let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
8578        assert_eq_m256i(r, e);
8579    }
8580
8581    #[simd_test(enable = "avx512f,avx512vl")]
8582    unsafe fn test_mm256_maskz_slli_epi64() {
8583        let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8584        let r = _mm256_maskz_slli_epi64::<1>(0, a);
8585        assert_eq_m256i(r, _mm256_setzero_si256());
8586        let r = _mm256_maskz_slli_epi64::<1>(0b00001111, a);
8587        let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
8588        assert_eq_m256i(r, e);
8589    }
8590
8591    #[simd_test(enable = "avx512f,avx512vl")]
8592    unsafe fn test_mm_mask_slli_epi64() {
8593        let a = _mm_set_epi64x(1 << 63, 1 << 32);
8594        let r = _mm_mask_slli_epi64::<1>(a, 0, a);
8595        assert_eq_m128i(r, a);
8596        let r = _mm_mask_slli_epi64::<1>(a, 0b00000011, a);
8597        let e = _mm_set_epi64x(0, 1 << 33);
8598        assert_eq_m128i(r, e);
8599    }
8600
8601    #[simd_test(enable = "avx512f,avx512vl")]
8602    unsafe fn test_mm_maskz_slli_epi64() {
8603        let a = _mm_set_epi64x(1 << 63, 1 << 32);
8604        let r = _mm_maskz_slli_epi64::<1>(0, a);
8605        assert_eq_m128i(r, _mm_setzero_si128());
8606        let r = _mm_maskz_slli_epi64::<1>(0b00000011, a);
8607        let e = _mm_set_epi64x(0, 1 << 33);
8608        assert_eq_m128i(r, e);
8609    }
8610
8611    #[simd_test(enable = "avx512f")]
8612    unsafe fn test_mm512_srli_epi64() {
8613        #[rustfmt::skip]
8614        let a = _mm512_set_epi64(
8615            1 << 0, 1 << 32, 1 << 32, 1 << 32,
8616            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8617        );
8618        let r = _mm512_srli_epi64::<1>(a);
8619        #[rustfmt::skip]
8620        let e = _mm512_set_epi64(
8621            0, 1 << 31, 1 << 31, 1 << 31,
8622            1 << 31, 1 << 31, 1 << 31, 1 << 31,
8623        );
8624        assert_eq_m512i(r, e);
8625    }
8626
8627    #[simd_test(enable = "avx512f")]
8628    unsafe fn test_mm512_mask_srli_epi64() {
8629        #[rustfmt::skip]
8630        let a = _mm512_set_epi64(
8631            1 << 0, 1 << 32, 1 << 32, 1 << 32,
8632            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8633        );
8634        let r = _mm512_mask_srli_epi64::<1>(a, 0, a);
8635        assert_eq_m512i(r, a);
8636        let r = _mm512_mask_srli_epi64::<1>(a, 0b11111111, a);
8637        #[rustfmt::skip]
8638        let e = _mm512_set_epi64(
8639            0, 1 << 31, 1 << 31, 1 << 31,
8640            1 << 31, 1 << 31, 1 << 31, 1 << 31,
8641        );
8642        assert_eq_m512i(r, e);
8643    }
8644
8645    #[simd_test(enable = "avx512f")]
8646    unsafe fn test_mm512_maskz_srli_epi64() {
8647        #[rustfmt::skip]
8648        let a = _mm512_set_epi64(
8649            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8650            1 << 32, 1 << 32, 1 << 32, 1 << 0,
8651        );
8652        let r = _mm512_maskz_srli_epi64::<1>(0, a);
8653        assert_eq_m512i(r, _mm512_setzero_si512());
8654        let r = _mm512_maskz_srli_epi64::<1>(0b00001111, a);
8655        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 0);
8656        assert_eq_m512i(r, e);
8657    }
8658
8659    #[simd_test(enable = "avx512f,avx512vl")]
8660    unsafe fn test_mm256_mask_srli_epi64() {
8661        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8662        let r = _mm256_mask_srli_epi64::<1>(a, 0, a);
8663        assert_eq_m256i(r, a);
8664        let r = _mm256_mask_srli_epi64::<1>(a, 0b00001111, a);
8665        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8666        assert_eq_m256i(r, e);
8667    }
8668
8669    #[simd_test(enable = "avx512f,avx512vl")]
8670    unsafe fn test_mm256_maskz_srli_epi64() {
8671        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8672        let r = _mm256_maskz_srli_epi64::<1>(0, a);
8673        assert_eq_m256i(r, _mm256_setzero_si256());
8674        let r = _mm256_maskz_srli_epi64::<1>(0b00001111, a);
8675        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8676        assert_eq_m256i(r, e);
8677    }
8678
8679    #[simd_test(enable = "avx512f,avx512vl")]
8680    unsafe fn test_mm_mask_srli_epi64() {
8681        let a = _mm_set_epi64x(1 << 5, 0);
8682        let r = _mm_mask_srli_epi64::<1>(a, 0, a);
8683        assert_eq_m128i(r, a);
8684        let r = _mm_mask_srli_epi64::<1>(a, 0b00000011, a);
8685        let e = _mm_set_epi64x(1 << 4, 0);
8686        assert_eq_m128i(r, e);
8687    }
8688
8689    #[simd_test(enable = "avx512f,avx512vl")]
8690    unsafe fn test_mm_maskz_srli_epi64() {
8691        let a = _mm_set_epi64x(1 << 5, 0);
8692        let r = _mm_maskz_srli_epi64::<1>(0, a);
8693        assert_eq_m128i(r, _mm_setzero_si128());
8694        let r = _mm_maskz_srli_epi64::<1>(0b00000011, a);
8695        let e = _mm_set_epi64x(1 << 4, 0);
8696        assert_eq_m128i(r, e);
8697    }
8698
8699    #[simd_test(enable = "avx512f")]
8700    unsafe fn test_mm512_rolv_epi64() {
8701        #[rustfmt::skip]
8702        let a = _mm512_set_epi64(
8703            1 << 32, 1 << 63, 1 << 32, 1 << 32,
8704            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8705        );
8706        let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8707        let r = _mm512_rolv_epi64(a, b);
8708        #[rustfmt::skip]
8709        let e = _mm512_set_epi64(
8710            1 << 32, 1 << 0,  1 << 34, 1 << 35,
8711            1 << 36, 1 << 37, 1 << 38, 1 << 39,
8712        );
8713        assert_eq_m512i(r, e);
8714    }
8715
8716    #[simd_test(enable = "avx512f")]
8717    unsafe fn test_mm512_mask_rolv_epi64() {
8718        #[rustfmt::skip]
8719        let a = _mm512_set_epi64(
8720            1 << 32, 1 << 63, 1 << 32, 1 << 32,
8721            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8722        );
8723        let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8724        let r = _mm512_mask_rolv_epi64(a, 0, a, b);
8725        assert_eq_m512i(r, a);
8726        let r = _mm512_mask_rolv_epi64(a, 0b11111111, a, b);
8727        #[rustfmt::skip]
8728        let e = _mm512_set_epi64(
8729            1 << 32, 1 << 0,  1 << 34, 1 << 35,
8730            1 << 36, 1 << 37, 1 << 38, 1 << 39,
8731        );
8732        assert_eq_m512i(r, e);
8733    }
8734
8735    #[simd_test(enable = "avx512f")]
8736    unsafe fn test_mm512_maskz_rolv_epi64() {
8737        #[rustfmt::skip]
8738        let a = _mm512_set_epi64(
8739            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8740            1 << 32, 1 << 32, 1 << 32, 1 << 62,
8741        );
8742        let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 2);
8743        let r = _mm512_maskz_rolv_epi64(0, a, b);
8744        assert_eq_m512i(r, _mm512_setzero_si512());
8745        let r = _mm512_maskz_rolv_epi64(0b00001111, a, b);
8746        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 36, 1 << 37, 1 << 38, 1 << 0);
8747        assert_eq_m512i(r, e);
8748    }
8749
8750    #[simd_test(enable = "avx512f,avx512vl")]
8751    unsafe fn test_mm256_rolv_epi64() {
8752        let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8753        let b = _mm256_set_epi64x(0, 1, 2, 3);
8754        let r = _mm256_rolv_epi64(a, b);
8755        let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8756        assert_eq_m256i(r, e);
8757    }
8758
8759    #[simd_test(enable = "avx512f,avx512vl")]
8760    unsafe fn test_mm256_mask_rolv_epi64() {
8761        let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8762        let b = _mm256_set_epi64x(0, 1, 2, 3);
8763        let r = _mm256_mask_rolv_epi64(a, 0, a, b);
8764        assert_eq_m256i(r, a);
8765        let r = _mm256_mask_rolv_epi64(a, 0b00001111, a, b);
8766        let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8767        assert_eq_m256i(r, e);
8768    }
8769
8770    #[simd_test(enable = "avx512f,avx512vl")]
8771    unsafe fn test_mm256_maskz_rolv_epi64() {
8772        let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8773        let b = _mm256_set_epi64x(0, 1, 2, 3);
8774        let r = _mm256_maskz_rolv_epi64(0, a, b);
8775        assert_eq_m256i(r, _mm256_setzero_si256());
8776        let r = _mm256_maskz_rolv_epi64(0b00001111, a, b);
8777        let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8778        assert_eq_m256i(r, e);
8779    }
8780
8781    #[simd_test(enable = "avx512f,avx512vl")]
8782    unsafe fn test_mm_rolv_epi64() {
8783        let a = _mm_set_epi64x(1 << 32, 1 << 63);
8784        let b = _mm_set_epi64x(0, 1);
8785        let r = _mm_rolv_epi64(a, b);
8786        let e = _mm_set_epi64x(1 << 32, 1 << 0);
8787        assert_eq_m128i(r, e);
8788    }
8789
8790    #[simd_test(enable = "avx512f,avx512vl")]
8791    unsafe fn test_mm_mask_rolv_epi64() {
8792        let a = _mm_set_epi64x(1 << 32, 1 << 63);
8793        let b = _mm_set_epi64x(0, 1);
8794        let r = _mm_mask_rolv_epi64(a, 0, a, b);
8795        assert_eq_m128i(r, a);
8796        let r = _mm_mask_rolv_epi64(a, 0b00000011, a, b);
8797        let e = _mm_set_epi64x(1 << 32, 1 << 0);
8798        assert_eq_m128i(r, e);
8799    }
8800
8801    #[simd_test(enable = "avx512f,avx512vl")]
8802    unsafe fn test_mm_maskz_rolv_epi64() {
8803        let a = _mm_set_epi64x(1 << 32, 1 << 63);
8804        let b = _mm_set_epi64x(0, 1);
8805        let r = _mm_maskz_rolv_epi64(0, a, b);
8806        assert_eq_m128i(r, _mm_setzero_si128());
8807        let r = _mm_maskz_rolv_epi64(0b00000011, a, b);
8808        let e = _mm_set_epi64x(1 << 32, 1 << 0);
8809        assert_eq_m128i(r, e);
8810    }
8811
8812    #[simd_test(enable = "avx512f")]
8813    unsafe fn test_mm512_rorv_epi64() {
8814        #[rustfmt::skip]
8815        let a = _mm512_set_epi64(
8816            1 << 32, 1 << 0, 1 << 32, 1 << 32,
8817            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8818        );
8819        let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8820        let r = _mm512_rorv_epi64(a, b);
8821        #[rustfmt::skip]
8822        let e = _mm512_set_epi64(
8823            1 << 32, 1 << 63, 1 << 30, 1 << 29,
8824            1 << 28, 1 << 27, 1 << 26, 1 << 25,
8825        );
8826        assert_eq_m512i(r, e);
8827    }
8828
8829    #[simd_test(enable = "avx512f")]
8830    unsafe fn test_mm512_mask_rorv_epi64() {
8831        #[rustfmt::skip]
8832        let a = _mm512_set_epi64(
8833            1 << 32, 1 << 0, 1 << 32, 1 << 32,
8834            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8835        );
8836        let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8837        let r = _mm512_mask_rorv_epi64(a, 0, a, b);
8838        assert_eq_m512i(r, a);
8839        let r = _mm512_mask_rorv_epi64(a, 0b11111111, a, b);
8840        #[rustfmt::skip]
8841        let e = _mm512_set_epi64(
8842            1 << 32, 1 << 63, 1 << 30, 1 << 29,
8843            1 << 28, 1 << 27, 1 << 26, 1 << 25,
8844        );
8845        assert_eq_m512i(r, e);
8846    }
8847
8848    #[simd_test(enable = "avx512f")]
8849    unsafe fn test_mm512_maskz_rorv_epi64() {
8850        #[rustfmt::skip]
8851        let a = _mm512_set_epi64(
8852            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8853            1 << 32, 1 << 32, 1 << 32, 1 << 0,
8854        );
8855        let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 2);
8856        let r = _mm512_maskz_rorv_epi64(0, a, b);
8857        assert_eq_m512i(r, _mm512_setzero_si512());
8858        let r = _mm512_maskz_rorv_epi64(0b00001111, a, b);
8859        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 28, 1 << 27, 1 << 26, 1 << 62);
8860        assert_eq_m512i(r, e);
8861    }
8862
8863    #[simd_test(enable = "avx512f,avx512vl")]
8864    unsafe fn test_mm256_rorv_epi64() {
8865        let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8866        let b = _mm256_set_epi64x(0, 1, 2, 3);
8867        let r = _mm256_rorv_epi64(a, b);
8868        let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8869        assert_eq_m256i(r, e);
8870    }
8871
8872    #[simd_test(enable = "avx512f,avx512vl")]
8873    unsafe fn test_mm256_mask_rorv_epi64() {
8874        let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8875        let b = _mm256_set_epi64x(0, 1, 2, 3);
8876        let r = _mm256_mask_rorv_epi64(a, 0, a, b);
8877        assert_eq_m256i(r, a);
8878        let r = _mm256_mask_rorv_epi64(a, 0b00001111, a, b);
8879        let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8880        assert_eq_m256i(r, e);
8881    }
8882
8883    #[simd_test(enable = "avx512f,avx512vl")]
8884    unsafe fn test_mm256_maskz_rorv_epi64() {
8885        let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8886        let b = _mm256_set_epi64x(0, 1, 2, 3);
8887        let r = _mm256_maskz_rorv_epi64(0, a, b);
8888        assert_eq_m256i(r, _mm256_setzero_si256());
8889        let r = _mm256_maskz_rorv_epi64(0b00001111, a, b);
8890        let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8891        assert_eq_m256i(r, e);
8892    }
8893
8894    #[simd_test(enable = "avx512f,avx512vl")]
8895    unsafe fn test_mm_rorv_epi64() {
8896        let a = _mm_set_epi64x(1 << 32, 1 << 0);
8897        let b = _mm_set_epi64x(0, 1);
8898        let r = _mm_rorv_epi64(a, b);
8899        let e = _mm_set_epi64x(1 << 32, 1 << 63);
8900        assert_eq_m128i(r, e);
8901    }
8902
8903    #[simd_test(enable = "avx512f,avx512vl")]
8904    unsafe fn test_mm_mask_rorv_epi64() {
8905        let a = _mm_set_epi64x(1 << 32, 1 << 0);
8906        let b = _mm_set_epi64x(0, 1);
8907        let r = _mm_mask_rorv_epi64(a, 0, a, b);
8908        assert_eq_m128i(r, a);
8909        let r = _mm_mask_rorv_epi64(a, 0b00000011, a, b);
8910        let e = _mm_set_epi64x(1 << 32, 1 << 63);
8911        assert_eq_m128i(r, e);
8912    }
8913
8914    #[simd_test(enable = "avx512f,avx512vl")]
8915    unsafe fn test_mm_maskz_rorv_epi64() {
8916        let a = _mm_set_epi64x(1 << 32, 1 << 0);
8917        let b = _mm_set_epi64x(0, 1);
8918        let r = _mm_maskz_rorv_epi64(0, a, b);
8919        assert_eq_m128i(r, _mm_setzero_si128());
8920        let r = _mm_maskz_rorv_epi64(0b00000011, a, b);
8921        let e = _mm_set_epi64x(1 << 32, 1 << 63);
8922        assert_eq_m128i(r, e);
8923    }
8924
8925    #[simd_test(enable = "avx512f")]
8926    unsafe fn test_mm512_sllv_epi64() {
8927        #[rustfmt::skip]
8928        let a = _mm512_set_epi64(
8929            1 << 32, 1 << 63, 1 << 32, 1 << 32,
8930            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8931        );
8932        let count = _mm512_set_epi64(0, 2, 2, 3, 4, 5, 6, 7);
8933        let r = _mm512_sllv_epi64(a, count);
8934        #[rustfmt::skip]
8935        let e = _mm512_set_epi64(
8936            1 << 32, 0, 1 << 34, 1 << 35,
8937            1 << 36, 1 << 37, 1 << 38, 1 << 39,
8938        );
8939        assert_eq_m512i(r, e);
8940    }
8941
8942    #[simd_test(enable = "avx512f")]
8943    unsafe fn test_mm512_mask_sllv_epi64() {
8944        #[rustfmt::skip]
8945        let a = _mm512_set_epi64(
8946            1 << 32, 1 << 32, 1 << 63, 1 << 32,
8947            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8948        );
8949        let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8950        let r = _mm512_mask_sllv_epi64(a, 0, a, count);
8951        assert_eq_m512i(r, a);
8952        let r = _mm512_mask_sllv_epi64(a, 0b11111111, a, count);
8953        #[rustfmt::skip]
8954        let e = _mm512_set_epi64(
8955            1 << 32, 1 << 33, 0, 1 << 35,
8956            1 << 36, 1 << 37, 1 << 38, 1 << 39,
8957        );
8958        assert_eq_m512i(r, e);
8959    }
8960
8961    #[simd_test(enable = "avx512f")]
8962    unsafe fn test_mm512_maskz_sllv_epi64() {
8963        #[rustfmt::skip]
8964        let a = _mm512_set_epi64(
8965            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8966            1 << 32, 1 << 32, 1 << 32, 1 << 63,
8967        );
8968        let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 1);
8969        let r = _mm512_maskz_sllv_epi64(0, a, count);
8970        assert_eq_m512i(r, _mm512_setzero_si512());
8971        let r = _mm512_maskz_sllv_epi64(0b00001111, a, count);
8972        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 36, 1 << 37, 1 << 38, 0);
8973        assert_eq_m512i(r, e);
8974    }
8975
8976    #[simd_test(enable = "avx512f,avx512vl")]
8977    unsafe fn test_mm256_mask_sllv_epi64() {
8978        let a = _mm256_set_epi64x(1 << 32, 1 << 32, 1 << 63, 1 << 32);
8979        let count = _mm256_set_epi64x(0, 1, 2, 3);
8980        let r = _mm256_mask_sllv_epi64(a, 0, a, count);
8981        assert_eq_m256i(r, a);
8982        let r = _mm256_mask_sllv_epi64(a, 0b00001111, a, count);
8983        let e = _mm256_set_epi64x(1 << 32, 1 << 33, 0, 1 << 35);
8984        assert_eq_m256i(r, e);
8985    }
8986
8987    #[simd_test(enable = "avx512f,avx512vl")]
8988    unsafe fn test_mm256_maskz_sllv_epi64() {
8989        let a = _mm256_set_epi64x(1 << 32, 1 << 32, 1 << 63, 1 << 32);
8990        let count = _mm256_set_epi64x(0, 1, 2, 3);
8991        let r = _mm256_maskz_sllv_epi64(0, a, count);
8992        assert_eq_m256i(r, _mm256_setzero_si256());
8993        let r = _mm256_maskz_sllv_epi64(0b00001111, a, count);
8994        let e = _mm256_set_epi64x(1 << 32, 1 << 33, 0, 1 << 35);
8995        assert_eq_m256i(r, e);
8996    }
8997
8998    #[simd_test(enable = "avx512f,avx512vl")]
8999    unsafe fn test_mm_mask_sllv_epi64() {
9000        let a = _mm_set_epi64x(1 << 63, 1 << 32);
9001        let count = _mm_set_epi64x(2, 3);
9002        let r = _mm_mask_sllv_epi64(a, 0, a, count);
9003        assert_eq_m128i(r, a);
9004        let r = _mm_mask_sllv_epi64(a, 0b00000011, a, count);
9005        let e = _mm_set_epi64x(0, 1 << 35);
9006        assert_eq_m128i(r, e);
9007    }
9008
9009    #[simd_test(enable = "avx512f,avx512vl")]
9010    unsafe fn test_mm_maskz_sllv_epi64() {
9011        let a = _mm_set_epi64x(1 << 63, 1 << 32);
9012        let count = _mm_set_epi64x(2, 3);
9013        let r = _mm_maskz_sllv_epi64(0, a, count);
9014        assert_eq_m128i(r, _mm_setzero_si128());
9015        let r = _mm_maskz_sllv_epi64(0b00000011, a, count);
9016        let e = _mm_set_epi64x(0, 1 << 35);
9017        assert_eq_m128i(r, e);
9018    }
9019
9020    #[simd_test(enable = "avx512f")]
9021    unsafe fn test_mm512_srlv_epi64() {
9022        #[rustfmt::skip]
9023        let a = _mm512_set_epi64(
9024            1 << 32, 1 << 0, 1 << 32, 1 << 32,
9025            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9026        );
9027        let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9028        let r = _mm512_srlv_epi64(a, count);
9029        #[rustfmt::skip]
9030        let e = _mm512_set_epi64(
9031            1 << 32, 0, 1 << 30, 1 << 29,
9032            1 << 28, 1 << 27, 1 << 26, 1 << 25,
9033        );
9034        assert_eq_m512i(r, e);
9035    }
9036
9037    #[simd_test(enable = "avx512f")]
9038    unsafe fn test_mm512_mask_srlv_epi64() {
9039        #[rustfmt::skip]
9040        let a = _mm512_set_epi64(
9041            1 << 32, 1 << 0, 1 << 32, 1 << 32,
9042            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9043        );
9044        let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9045        let r = _mm512_mask_srlv_epi64(a, 0, a, count);
9046        assert_eq_m512i(r, a);
9047        let r = _mm512_mask_srlv_epi64(a, 0b11111111, a, count);
9048        #[rustfmt::skip]
9049        let e = _mm512_set_epi64(
9050            1 << 32, 0, 1 << 30, 1 << 29,
9051            1 << 28, 1 << 27, 1 << 26, 1 << 25,
9052        );
9053        assert_eq_m512i(r, e);
9054    }
9055
9056    #[simd_test(enable = "avx512f")]
9057    unsafe fn test_mm512_maskz_srlv_epi64() {
9058        #[rustfmt::skip]
9059        let a = _mm512_set_epi64(
9060            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9061            1 << 32, 1 << 32, 1 << 32, 1 << 0,
9062        );
9063        let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9064        let r = _mm512_maskz_srlv_epi64(0, a, count);
9065        assert_eq_m512i(r, _mm512_setzero_si512());
9066        let r = _mm512_maskz_srlv_epi64(0b00001111, a, count);
9067        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 28, 1 << 27, 1 << 26, 0);
9068        assert_eq_m512i(r, e);
9069    }
9070
9071    #[simd_test(enable = "avx512f,avx512vl")]
9072    unsafe fn test_mm256_mask_srlv_epi64() {
9073        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9074        let count = _mm256_set1_epi64x(1);
9075        let r = _mm256_mask_srlv_epi64(a, 0, a, count);
9076        assert_eq_m256i(r, a);
9077        let r = _mm256_mask_srlv_epi64(a, 0b00001111, a, count);
9078        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9079        assert_eq_m256i(r, e);
9080    }
9081
9082    #[simd_test(enable = "avx512f,avx512vl")]
9083    unsafe fn test_mm256_maskz_srlv_epi64() {
9084        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9085        let count = _mm256_set1_epi64x(1);
9086        let r = _mm256_maskz_srlv_epi64(0, a, count);
9087        assert_eq_m256i(r, _mm256_setzero_si256());
9088        let r = _mm256_maskz_srlv_epi64(0b00001111, a, count);
9089        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9090        assert_eq_m256i(r, e);
9091    }
9092
9093    #[simd_test(enable = "avx512f,avx512vl")]
9094    unsafe fn test_mm_mask_srlv_epi64() {
9095        let a = _mm_set_epi64x(1 << 5, 0);
9096        let count = _mm_set1_epi64x(1);
9097        let r = _mm_mask_srlv_epi64(a, 0, a, count);
9098        assert_eq_m128i(r, a);
9099        let r = _mm_mask_srlv_epi64(a, 0b00000011, a, count);
9100        let e = _mm_set_epi64x(1 << 4, 0);
9101        assert_eq_m128i(r, e);
9102    }
9103
9104    #[simd_test(enable = "avx512f,avx512vl")]
9105    unsafe fn test_mm_maskz_srlv_epi64() {
9106        let a = _mm_set_epi64x(1 << 5, 0);
9107        let count = _mm_set1_epi64x(1);
9108        let r = _mm_maskz_srlv_epi64(0, a, count);
9109        assert_eq_m128i(r, _mm_setzero_si128());
9110        let r = _mm_maskz_srlv_epi64(0b00000011, a, count);
9111        let e = _mm_set_epi64x(1 << 4, 0);
9112        assert_eq_m128i(r, e);
9113    }
9114
9115    #[simd_test(enable = "avx512f")]
9116    unsafe fn test_mm512_sll_epi64() {
9117        #[rustfmt::skip]
9118        let a = _mm512_set_epi64(
9119            1 << 63, 1 << 32, 1 << 32, 1 << 32,
9120            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9121        );
9122        let count = _mm_set_epi64x(0, 1);
9123        let r = _mm512_sll_epi64(a, count);
9124        #[rustfmt::skip]
9125        let e = _mm512_set_epi64(
9126            0, 1 << 33, 1 << 33, 1 << 33,
9127            1 << 33, 1 << 33, 1 << 33, 1 << 33,
9128        );
9129        assert_eq_m512i(r, e);
9130        let count = _mm_set_epi64x(1, 0);
9131        let r = _mm512_sll_epi64(a, count);
9132        assert_eq_m512i(r, a);
9133    }
9134
9135    #[simd_test(enable = "avx512f")]
9136    unsafe fn test_mm512_mask_sll_epi64() {
9137        #[rustfmt::skip]
9138        let a = _mm512_set_epi64(
9139            1 << 63, 1 << 32, 1 << 32, 1 << 32,
9140            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9141        );
9142        let count = _mm_set_epi64x(0, 1);
9143        let r = _mm512_mask_sll_epi64(a, 0, a, count);
9144        assert_eq_m512i(r, a);
9145        let r = _mm512_mask_sll_epi64(a, 0b11111111, a, count);
9146        #[rustfmt::skip]
9147        let e = _mm512_set_epi64(
9148            0, 1 << 33, 1 << 33, 1 << 33,
9149            1 << 33, 1 << 33, 1 << 33, 1 << 33,
9150        );
9151        assert_eq_m512i(r, e);
9152    }
9153
9154    #[simd_test(enable = "avx512f")]
9155    unsafe fn test_mm512_maskz_sll_epi64() {
9156        #[rustfmt::skip]
9157        let a = _mm512_set_epi64(
9158            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9159            1 << 32, 1 << 32, 1 << 32, 1 << 63,
9160        );
9161        let count = _mm_set_epi64x(0, 1);
9162        let r = _mm512_maskz_sll_epi64(0, a, count);
9163        assert_eq_m512i(r, _mm512_setzero_si512());
9164        let r = _mm512_maskz_sll_epi64(0b00001111, a, count);
9165        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 0);
9166        assert_eq_m512i(r, e);
9167    }
9168
9169    #[simd_test(enable = "avx512f,avx512vl")]
9170    unsafe fn test_mm256_mask_sll_epi64() {
9171        let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
9172        let count = _mm_set_epi64x(0, 1);
9173        let r = _mm256_mask_sll_epi64(a, 0, a, count);
9174        assert_eq_m256i(r, a);
9175        let r = _mm256_mask_sll_epi64(a, 0b00001111, a, count);
9176        let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
9177        assert_eq_m256i(r, e);
9178    }
9179
9180    #[simd_test(enable = "avx512f,avx512vl")]
9181    unsafe fn test_mm256_maskz_sll_epi64() {
9182        let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
9183        let count = _mm_set_epi64x(0, 1);
9184        let r = _mm256_maskz_sll_epi64(0, a, count);
9185        assert_eq_m256i(r, _mm256_setzero_si256());
9186        let r = _mm256_maskz_sll_epi64(0b00001111, a, count);
9187        let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
9188        assert_eq_m256i(r, e);
9189    }
9190
9191    #[simd_test(enable = "avx512f,avx512vl")]
9192    unsafe fn test_mm_mask_sll_epi64() {
9193        let a = _mm_set_epi64x(1 << 63, 1 << 32);
9194        let count = _mm_set_epi64x(0, 1);
9195        let r = _mm_mask_sll_epi64(a, 0, a, count);
9196        assert_eq_m128i(r, a);
9197        let r = _mm_mask_sll_epi64(a, 0b00000011, a, count);
9198        let e = _mm_set_epi64x(0, 1 << 33);
9199        assert_eq_m128i(r, e);
9200    }
9201
9202    #[simd_test(enable = "avx512f,avx512vl")]
9203    unsafe fn test_mm_maskz_sll_epi64() {
9204        let a = _mm_set_epi64x(1 << 63, 1 << 32);
9205        let count = _mm_set_epi64x(0, 1);
9206        let r = _mm_maskz_sll_epi64(0, a, count);
9207        assert_eq_m128i(r, _mm_setzero_si128());
9208        let r = _mm_maskz_sll_epi64(0b00000011, a, count);
9209        let e = _mm_set_epi64x(0, 1 << 33);
9210        assert_eq_m128i(r, e);
9211    }
9212
9213    #[simd_test(enable = "avx512f")]
9214    unsafe fn test_mm512_srl_epi64() {
9215        #[rustfmt::skip]
9216        let a = _mm512_set_epi64(
9217            1 << 0, 1 << 32, 1 << 32, 1 << 32,
9218            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9219        );
9220        let count = _mm_set_epi64x(0, 1);
9221        let r = _mm512_srl_epi64(a, count);
9222        #[rustfmt::skip]
9223        let e = _mm512_set_epi64(
9224            0, 1 << 31, 1 << 31, 1 << 31,
9225            1 << 31, 1 << 31, 1 << 31, 1 << 31,
9226        );
9227        assert_eq_m512i(r, e);
9228    }
9229
9230    #[simd_test(enable = "avx512f")]
9231    unsafe fn test_mm512_mask_srl_epi64() {
9232        #[rustfmt::skip]
9233        let a = _mm512_set_epi64(
9234            1 << 0, 1 << 32, 1 << 32, 1 << 32,
9235            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9236        );
9237        let count = _mm_set_epi64x(0, 1);
9238        let r = _mm512_mask_srl_epi64(a, 0, a, count);
9239        assert_eq_m512i(r, a);
9240        let r = _mm512_mask_srl_epi64(a, 0b11111111, a, count);
9241        #[rustfmt::skip]
9242        let e = _mm512_set_epi64(
9243            0, 1 << 31, 1 << 31, 1 << 31,
9244            1 << 31, 1 << 31, 1 << 31, 1 << 31,
9245        );
9246        assert_eq_m512i(r, e);
9247    }
9248
9249    #[simd_test(enable = "avx512f")]
9250    unsafe fn test_mm512_maskz_srl_epi64() {
9251        #[rustfmt::skip]
9252        let a = _mm512_set_epi64(
9253            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9254            1 << 32, 1 << 32, 1 << 32, 1 << 0,
9255        );
9256        let count = _mm_set_epi64x(0, 1);
9257        let r = _mm512_maskz_srl_epi64(0, a, count);
9258        assert_eq_m512i(r, _mm512_setzero_si512());
9259        let r = _mm512_maskz_srl_epi64(0b00001111, a, count);
9260        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 0);
9261        assert_eq_m512i(r, e);
9262    }
9263
9264    #[simd_test(enable = "avx512f,avx512vl")]
9265    unsafe fn test_mm256_mask_srl_epi64() {
9266        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9267        let count = _mm_set_epi64x(0, 1);
9268        let r = _mm256_mask_srl_epi64(a, 0, a, count);
9269        assert_eq_m256i(r, a);
9270        let r = _mm256_mask_srl_epi64(a, 0b00001111, a, count);
9271        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9272        assert_eq_m256i(r, e);
9273    }
9274
9275    #[simd_test(enable = "avx512f,avx512vl")]
9276    unsafe fn test_mm256_maskz_srl_epi64() {
9277        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9278        let count = _mm_set_epi64x(0, 1);
9279        let r = _mm256_maskz_srl_epi64(0, a, count);
9280        assert_eq_m256i(r, _mm256_setzero_si256());
9281        let r = _mm256_maskz_srl_epi64(0b00001111, a, count);
9282        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9283        assert_eq_m256i(r, e);
9284    }
9285
9286    #[simd_test(enable = "avx512f,avx512vl")]
9287    unsafe fn test_mm_mask_srl_epi64() {
9288        let a = _mm_set_epi64x(1 << 5, 0);
9289        let count = _mm_set_epi64x(0, 1);
9290        let r = _mm_mask_srl_epi64(a, 0, a, count);
9291        assert_eq_m128i(r, a);
9292        let r = _mm_mask_srl_epi64(a, 0b00000011, a, count);
9293        let e = _mm_set_epi64x(1 << 4, 0);
9294        assert_eq_m128i(r, e);
9295    }
9296
9297    #[simd_test(enable = "avx512f,avx512vl")]
9298    unsafe fn test_mm_maskz_srl_epi64() {
9299        let a = _mm_set_epi64x(1 << 5, 0);
9300        let count = _mm_set_epi64x(0, 1);
9301        let r = _mm_maskz_srl_epi64(0, a, count);
9302        assert_eq_m128i(r, _mm_setzero_si128());
9303        let r = _mm_maskz_srl_epi64(0b00000011, a, count);
9304        let e = _mm_set_epi64x(1 << 4, 0);
9305        assert_eq_m128i(r, e);
9306    }
9307
9308    #[simd_test(enable = "avx512f")]
9309    unsafe fn test_mm512_sra_epi64() {
9310        let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9311        let count = _mm_set_epi64x(0, 2);
9312        let r = _mm512_sra_epi64(a, count);
9313        let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -4);
9314        assert_eq_m512i(r, e);
9315    }
9316
9317    #[simd_test(enable = "avx512f")]
9318    unsafe fn test_mm512_mask_sra_epi64() {
9319        let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9320        let count = _mm_set_epi64x(0, 2);
9321        let r = _mm512_mask_sra_epi64(a, 0, a, count);
9322        assert_eq_m512i(r, a);
9323        let r = _mm512_mask_sra_epi64(a, 0b11111111, a, count);
9324        let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -4);
9325        assert_eq_m512i(r, e);
9326    }
9327
9328    #[simd_test(enable = "avx512f")]
9329    unsafe fn test_mm512_maskz_sra_epi64() {
9330        let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9331        let count = _mm_set_epi64x(0, 2);
9332        let r = _mm512_maskz_sra_epi64(0, a, count);
9333        assert_eq_m512i(r, _mm512_setzero_si512());
9334        let r = _mm512_maskz_sra_epi64(0b00001111, a, count);
9335        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 3, -4);
9336        assert_eq_m512i(r, e);
9337    }
9338
9339    #[simd_test(enable = "avx512f,avx512vl")]
9340    unsafe fn test_mm256_sra_epi64() {
9341        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9342        let count = _mm_set_epi64x(0, 1);
9343        let r = _mm256_sra_epi64(a, count);
9344        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9345        assert_eq_m256i(r, e);
9346    }
9347
9348    #[simd_test(enable = "avx512f,avx512vl")]
9349    unsafe fn test_mm256_mask_sra_epi64() {
9350        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9351        let count = _mm_set_epi64x(0, 1);
9352        let r = _mm256_mask_sra_epi64(a, 0, a, count);
9353        assert_eq_m256i(r, a);
9354        let r = _mm256_mask_sra_epi64(a, 0b00001111, a, count);
9355        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9356        assert_eq_m256i(r, e);
9357    }
9358
9359    #[simd_test(enable = "avx512f,avx512vl")]
9360    unsafe fn test_mm256_maskz_sra_epi64() {
9361        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9362        let count = _mm_set_epi64x(0, 1);
9363        let r = _mm256_maskz_sra_epi64(0, a, count);
9364        assert_eq_m256i(r, _mm256_setzero_si256());
9365        let r = _mm256_maskz_sra_epi64(0b00001111, a, count);
9366        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9367        assert_eq_m256i(r, e);
9368    }
9369
9370    #[simd_test(enable = "avx512f,avx512vl")]
9371    unsafe fn test_mm_sra_epi64() {
9372        let a = _mm_set_epi64x(1 << 5, 0);
9373        let count = _mm_set_epi64x(0, 1);
9374        let r = _mm_sra_epi64(a, count);
9375        let e = _mm_set_epi64x(1 << 4, 0);
9376        assert_eq_m128i(r, e);
9377    }
9378
9379    #[simd_test(enable = "avx512f,avx512vl")]
9380    unsafe fn test_mm_mask_sra_epi64() {
9381        let a = _mm_set_epi64x(1 << 5, 0);
9382        let count = _mm_set_epi64x(0, 1);
9383        let r = _mm_mask_sra_epi64(a, 0, a, count);
9384        assert_eq_m128i(r, a);
9385        let r = _mm_mask_sra_epi64(a, 0b00000011, a, count);
9386        let e = _mm_set_epi64x(1 << 4, 0);
9387        assert_eq_m128i(r, e);
9388    }
9389
9390    #[simd_test(enable = "avx512f,avx512vl")]
9391    unsafe fn test_mm_maskz_sra_epi64() {
9392        let a = _mm_set_epi64x(1 << 5, 0);
9393        let count = _mm_set_epi64x(0, 1);
9394        let r = _mm_maskz_sra_epi64(0, a, count);
9395        assert_eq_m128i(r, _mm_setzero_si128());
9396        let r = _mm_maskz_sra_epi64(0b00000011, a, count);
9397        let e = _mm_set_epi64x(1 << 4, 0);
9398        assert_eq_m128i(r, e);
9399    }
9400
9401    #[simd_test(enable = "avx512f")]
9402    unsafe fn test_mm512_srav_epi64() {
9403        let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9404        let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
9405        let r = _mm512_srav_epi64(a, count);
9406        let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -8);
9407        assert_eq_m512i(r, e);
9408    }
9409
9410    #[simd_test(enable = "avx512f")]
9411    unsafe fn test_mm512_mask_srav_epi64() {
9412        let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9413        let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
9414        let r = _mm512_mask_srav_epi64(a, 0, a, count);
9415        assert_eq_m512i(r, a);
9416        let r = _mm512_mask_srav_epi64(a, 0b11111111, a, count);
9417        let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -8);
9418        assert_eq_m512i(r, e);
9419    }
9420
9421    #[simd_test(enable = "avx512f")]
9422    unsafe fn test_mm512_maskz_srav_epi64() {
9423        let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9424        let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
9425        let r = _mm512_maskz_srav_epi64(0, a, count);
9426        assert_eq_m512i(r, _mm512_setzero_si512());
9427        let r = _mm512_maskz_srav_epi64(0b00001111, a, count);
9428        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 3, -8);
9429        assert_eq_m512i(r, e);
9430    }
9431
9432    #[simd_test(enable = "avx512f,avx512vl")]
9433    unsafe fn test_mm256_srav_epi64() {
9434        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9435        let count = _mm256_set1_epi64x(1);
9436        let r = _mm256_srav_epi64(a, count);
9437        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9438        assert_eq_m256i(r, e);
9439    }
9440
9441    #[simd_test(enable = "avx512f,avx512vl")]
9442    unsafe fn test_mm256_mask_srav_epi64() {
9443        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9444        let count = _mm256_set1_epi64x(1);
9445        let r = _mm256_mask_srav_epi64(a, 0, a, count);
9446        assert_eq_m256i(r, a);
9447        let r = _mm256_mask_srav_epi64(a, 0b00001111, a, count);
9448        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9449        assert_eq_m256i(r, e);
9450    }
9451
9452    #[simd_test(enable = "avx512f,avx512vl")]
9453    unsafe fn test_mm256_maskz_srav_epi64() {
9454        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9455        let count = _mm256_set1_epi64x(1);
9456        let r = _mm256_maskz_srav_epi64(0, a, count);
9457        assert_eq_m256i(r, _mm256_setzero_si256());
9458        let r = _mm256_maskz_srav_epi64(0b00001111, a, count);
9459        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9460        assert_eq_m256i(r, e);
9461    }
9462
9463    #[simd_test(enable = "avx512f,avx512vl")]
9464    unsafe fn test_mm_srav_epi64() {
9465        let a = _mm_set_epi64x(1 << 5, 0);
9466        let count = _mm_set1_epi64x(1);
9467        let r = _mm_srav_epi64(a, count);
9468        let e = _mm_set_epi64x(1 << 4, 0);
9469        assert_eq_m128i(r, e);
9470    }
9471
9472    #[simd_test(enable = "avx512f,avx512vl")]
9473    unsafe fn test_mm_mask_srav_epi64() {
9474        let a = _mm_set_epi64x(1 << 5, 0);
9475        let count = _mm_set1_epi64x(1);
9476        let r = _mm_mask_srav_epi64(a, 0, a, count);
9477        assert_eq_m128i(r, a);
9478        let r = _mm_mask_srav_epi64(a, 0b00000011, a, count);
9479        let e = _mm_set_epi64x(1 << 4, 0);
9480        assert_eq_m128i(r, e);
9481    }
9482
9483    #[simd_test(enable = "avx512f,avx512vl")]
9484    unsafe fn test_mm_maskz_srav_epi64() {
9485        let a = _mm_set_epi64x(1 << 5, 0);
9486        let count = _mm_set1_epi64x(1);
9487        let r = _mm_maskz_srav_epi64(0, a, count);
9488        assert_eq_m128i(r, _mm_setzero_si128());
9489        let r = _mm_maskz_srav_epi64(0b00000011, a, count);
9490        let e = _mm_set_epi64x(1 << 4, 0);
9491        assert_eq_m128i(r, e);
9492    }
9493
9494    #[simd_test(enable = "avx512f")]
9495    unsafe fn test_mm512_srai_epi64() {
9496        let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
9497        let r = _mm512_srai_epi64::<2>(a);
9498        let e = _mm512_set_epi64(0, -1, 3, 0, 0, 0, 0, -4);
9499        assert_eq_m512i(r, e);
9500    }
9501
9502    #[simd_test(enable = "avx512f")]
9503    unsafe fn test_mm512_mask_srai_epi64() {
9504        let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
9505        let r = _mm512_mask_srai_epi64::<2>(a, 0, a);
9506        assert_eq_m512i(r, a);
9507        let r = _mm512_mask_srai_epi64::<2>(a, 0b11111111, a);
9508        let e = _mm512_set_epi64(0, -1, 3, 0, 0, 0, 0, -4);
9509        assert_eq_m512i(r, e);
9510    }
9511
9512    #[simd_test(enable = "avx512f")]
9513    unsafe fn test_mm512_maskz_srai_epi64() {
9514        let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
9515        let r = _mm512_maskz_srai_epi64::<2>(0, a);
9516        assert_eq_m512i(r, _mm512_setzero_si512());
9517        let r = _mm512_maskz_srai_epi64::<2>(0b00001111, a);
9518        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, -4);
9519        assert_eq_m512i(r, e);
9520    }
9521
9522    #[simd_test(enable = "avx512f,avx512vl")]
9523    unsafe fn test_mm256_srai_epi64() {
9524        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9525        let r = _mm256_srai_epi64::<1>(a);
9526        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9527        assert_eq_m256i(r, e);
9528    }
9529
9530    #[simd_test(enable = "avx512f,avx512vl")]
9531    unsafe fn test_mm256_mask_srai_epi64() {
9532        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9533        let r = _mm256_mask_srai_epi64::<1>(a, 0, a);
9534        assert_eq_m256i(r, a);
9535        let r = _mm256_mask_srai_epi64::<1>(a, 0b00001111, a);
9536        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9537        assert_eq_m256i(r, e);
9538    }
9539
9540    #[simd_test(enable = "avx512f,avx512vl")]
9541    unsafe fn test_mm256_maskz_srai_epi64() {
9542        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9543        let r = _mm256_maskz_srai_epi64::<1>(0, a);
9544        assert_eq_m256i(r, _mm256_setzero_si256());
9545        let r = _mm256_maskz_srai_epi64::<1>(0b00001111, a);
9546        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9547        assert_eq_m256i(r, e);
9548    }
9549
9550    #[simd_test(enable = "avx512f,avx512vl")]
9551    unsafe fn test_mm_srai_epi64() {
9552        let a = _mm_set_epi64x(1 << 5, 0);
9553        let r = _mm_srai_epi64::<1>(a);
9554        let e = _mm_set_epi64x(1 << 4, 0);
9555        assert_eq_m128i(r, e);
9556    }
9557
9558    #[simd_test(enable = "avx512f,avx512vl")]
9559    unsafe fn test_mm_mask_srai_epi64() {
9560        let a = _mm_set_epi64x(1 << 5, 0);
9561        let r = _mm_mask_srai_epi64::<1>(a, 0, a);
9562        assert_eq_m128i(r, a);
9563        let r = _mm_mask_srai_epi64::<1>(a, 0b00000011, a);
9564        let e = _mm_set_epi64x(1 << 4, 0);
9565        assert_eq_m128i(r, e);
9566    }
9567
9568    #[simd_test(enable = "avx512f,avx512vl")]
9569    unsafe fn test_mm_maskz_srai_epi64() {
9570        let a = _mm_set_epi64x(1 << 5, 0);
9571        let r = _mm_maskz_srai_epi64::<1>(0, a);
9572        assert_eq_m128i(r, _mm_setzero_si128());
9573        let r = _mm_maskz_srai_epi64::<1>(0b00000011, a);
9574        let e = _mm_set_epi64x(1 << 4, 0);
9575        assert_eq_m128i(r, e);
9576    }
9577
9578    #[simd_test(enable = "avx512f")]
9579    unsafe fn test_mm512_permute_pd() {
9580        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9581        let r = _mm512_permute_pd::<0b11_11_11_11>(a);
9582        let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9583        assert_eq_m512d(r, e);
9584    }
9585
9586    #[simd_test(enable = "avx512f")]
9587    unsafe fn test_mm512_mask_permute_pd() {
9588        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9589        let r = _mm512_mask_permute_pd::<0b11_11_11_11>(a, 0, a);
9590        assert_eq_m512d(r, a);
9591        let r = _mm512_mask_permute_pd::<0b11_11_11_11>(a, 0b11111111, a);
9592        let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9593        assert_eq_m512d(r, e);
9594    }
9595
9596    #[simd_test(enable = "avx512f")]
9597    unsafe fn test_mm512_maskz_permute_pd() {
9598        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9599        let r = _mm512_maskz_permute_pd::<0b11_11_11_11>(0, a);
9600        assert_eq_m512d(r, _mm512_setzero_pd());
9601        let r = _mm512_maskz_permute_pd::<0b11_11_11_11>(0b11111111, a);
9602        let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9603        assert_eq_m512d(r, e);
9604    }
9605
9606    #[simd_test(enable = "avx512f,avx512vl")]
9607    unsafe fn test_mm256_mask_permute_pd() {
9608        let a = _mm256_set_pd(3., 2., 1., 0.);
9609        let r = _mm256_mask_permute_pd::<0b11_11>(a, 0, a);
9610        assert_eq_m256d(r, a);
9611        let r = _mm256_mask_permute_pd::<0b11_11>(a, 0b00001111, a);
9612        let e = _mm256_set_pd(3., 3., 1., 1.);
9613        assert_eq_m256d(r, e);
9614    }
9615
9616    #[simd_test(enable = "avx512f,avx512vl")]
9617    unsafe fn test_mm256_maskz_permute_pd() {
9618        let a = _mm256_set_pd(3., 2., 1., 0.);
9619        let r = _mm256_maskz_permute_pd::<0b11_11>(0, a);
9620        assert_eq_m256d(r, _mm256_setzero_pd());
9621        let r = _mm256_maskz_permute_pd::<0b11_11>(0b00001111, a);
9622        let e = _mm256_set_pd(3., 3., 1., 1.);
9623        assert_eq_m256d(r, e);
9624    }
9625
9626    #[simd_test(enable = "avx512f,avx512vl")]
9627    unsafe fn test_mm_mask_permute_pd() {
9628        let a = _mm_set_pd(1., 0.);
9629        let r = _mm_mask_permute_pd::<0b11>(a, 0, a);
9630        assert_eq_m128d(r, a);
9631        let r = _mm_mask_permute_pd::<0b11>(a, 0b00000011, a);
9632        let e = _mm_set_pd(1., 1.);
9633        assert_eq_m128d(r, e);
9634    }
9635
9636    #[simd_test(enable = "avx512f,avx512vl")]
9637    unsafe fn test_mm_maskz_permute_pd() {
9638        let a = _mm_set_pd(1., 0.);
9639        let r = _mm_maskz_permute_pd::<0b11>(0, a);
9640        assert_eq_m128d(r, _mm_setzero_pd());
9641        let r = _mm_maskz_permute_pd::<0b11>(0b00000011, a);
9642        let e = _mm_set_pd(1., 1.);
9643        assert_eq_m128d(r, e);
9644    }
9645
9646    #[simd_test(enable = "avx512f")]
9647    unsafe fn test_mm512_permutex_epi64() {
9648        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9649        let r = _mm512_permutex_epi64::<0b11_11_11_11>(a);
9650        let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
9651        assert_eq_m512i(r, e);
9652    }
9653
9654    #[simd_test(enable = "avx512f")]
9655    unsafe fn test_mm512_mask_permutex_epi64() {
9656        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9657        let r = _mm512_mask_permutex_epi64::<0b11_11_11_11>(a, 0, a);
9658        assert_eq_m512i(r, a);
9659        let r = _mm512_mask_permutex_epi64::<0b11_11_11_11>(a, 0b11111111, a);
9660        let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
9661        assert_eq_m512i(r, e);
9662    }
9663
9664    #[simd_test(enable = "avx512f")]
9665    unsafe fn test_mm512_maskz_permutex_epi64() {
9666        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9667        let r = _mm512_maskz_permutex_epi64::<0b11_11_11_11>(0, a);
9668        assert_eq_m512i(r, _mm512_setzero_si512());
9669        let r = _mm512_maskz_permutex_epi64::<0b11_11_11_11>(0b11111111, a);
9670        let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
9671        assert_eq_m512i(r, e);
9672    }
9673
9674    #[simd_test(enable = "avx512f,avx512vl")]
9675    unsafe fn test_mm256_permutex_epi64() {
9676        let a = _mm256_set_epi64x(3, 2, 1, 0);
9677        let r = _mm256_permutex_epi64::<0b11_11_11_11>(a);
9678        let e = _mm256_set_epi64x(3, 3, 3, 3);
9679        assert_eq_m256i(r, e);
9680    }
9681
9682    #[simd_test(enable = "avx512f,avx512vl")]
9683    unsafe fn test_mm256_mask_permutex_epi64() {
9684        let a = _mm256_set_epi64x(3, 2, 1, 0);
9685        let r = _mm256_mask_permutex_epi64::<0b11_11_11_11>(a, 0, a);
9686        assert_eq_m256i(r, a);
9687        let r = _mm256_mask_permutex_epi64::<0b11_11_11_11>(a, 0b00001111, a);
9688        let e = _mm256_set_epi64x(3, 3, 3, 3);
9689        assert_eq_m256i(r, e);
9690    }
9691
9692    #[simd_test(enable = "avx512f,avx512vl")]
9693    unsafe fn test_mm256_maskz_permutex_epi64() {
9694        let a = _mm256_set_epi64x(3, 2, 1, 0);
9695        let r = _mm256_maskz_permutex_epi64::<0b11_11_11_11>(0, a);
9696        assert_eq_m256i(r, _mm256_setzero_si256());
9697        let r = _mm256_maskz_permutex_epi64::<0b11_11_11_11>(0b00001111, a);
9698        let e = _mm256_set_epi64x(3, 3, 3, 3);
9699        assert_eq_m256i(r, e);
9700    }
9701
9702    #[simd_test(enable = "avx512f")]
9703    unsafe fn test_mm512_permutex_pd() {
9704        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9705        let r = _mm512_permutex_pd::<0b11_11_11_11>(a);
9706        let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9707        assert_eq_m512d(r, e);
9708    }
9709
9710    #[simd_test(enable = "avx512f")]
9711    unsafe fn test_mm512_mask_permutex_pd() {
9712        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9713        let r = _mm512_mask_permutex_pd::<0b11_11_11_11>(a, 0, a);
9714        assert_eq_m512d(r, a);
9715        let r = _mm512_mask_permutex_pd::<0b11_11_11_11>(a, 0b11111111, a);
9716        let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9717        assert_eq_m512d(r, e);
9718    }
9719
9720    #[simd_test(enable = "avx512f")]
9721    unsafe fn test_mm512_maskz_permutex_pd() {
9722        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9723        let r = _mm512_maskz_permutex_pd::<0b11_11_11_11>(0, a);
9724        assert_eq_m512d(r, _mm512_setzero_pd());
9725        let r = _mm512_maskz_permutex_pd::<0b11_11_11_11>(0b11111111, a);
9726        let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9727        assert_eq_m512d(r, e);
9728    }
9729
9730    #[simd_test(enable = "avx512f,avx512vl")]
9731    unsafe fn test_mm256_permutex_pd() {
9732        let a = _mm256_set_pd(0., 1., 2., 3.);
9733        let r = _mm256_permutex_pd::<0b11_11_11_11>(a);
9734        let e = _mm256_set_pd(0., 0., 0., 0.);
9735        assert_eq_m256d(r, e);
9736    }
9737
9738    #[simd_test(enable = "avx512f,avx512vl")]
9739    unsafe fn test_mm256_mask_permutex_pd() {
9740        let a = _mm256_set_pd(0., 1., 2., 3.);
9741        let r = _mm256_mask_permutex_pd::<0b11_11_11_11>(a, 0, a);
9742        assert_eq_m256d(r, a);
9743        let r = _mm256_mask_permutex_pd::<0b11_11_11_11>(a, 0b00001111, a);
9744        let e = _mm256_set_pd(0., 0., 0., 0.);
9745        assert_eq_m256d(r, e);
9746    }
9747
9748    #[simd_test(enable = "avx512f,avx512vl")]
9749    unsafe fn test_mm256_maskz_permutex_pd() {
9750        let a = _mm256_set_pd(0., 1., 2., 3.);
9751        let r = _mm256_maskz_permutex_pd::<0b11_11_11_11>(0, a);
9752        assert_eq_m256d(r, _mm256_setzero_pd());
9753        let r = _mm256_maskz_permutex_pd::<0b11_11_11_11>(0b00001111, a);
9754        let e = _mm256_set_pd(0., 0., 0., 0.);
9755        assert_eq_m256d(r, e);
9756    }
9757
9758    #[simd_test(enable = "avx512f")]
9759    unsafe fn test_mm512_permutevar_pd() {
9760        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9761        let b = _mm512_set1_epi64(0b1);
9762        let r = _mm512_permutevar_pd(a, b);
9763        let e = _mm512_set_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9764        assert_eq_m512d(r, e);
9765    }
9766
9767    #[simd_test(enable = "avx512f")]
9768    unsafe fn test_mm512_mask_permutevar_pd() {
9769        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9770        let b = _mm512_set1_epi64(0b1);
9771        let r = _mm512_mask_permutevar_pd(a, 0, a, b);
9772        assert_eq_m512d(r, a);
9773        let r = _mm512_mask_permutevar_pd(a, 0b11111111, a, b);
9774        let e = _mm512_set_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9775        assert_eq_m512d(r, e);
9776    }
9777
9778    #[simd_test(enable = "avx512f")]
9779    unsafe fn test_mm512_maskz_permutevar_pd() {
9780        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9781        let b = _mm512_set1_epi64(0b1);
9782        let r = _mm512_maskz_permutevar_pd(0, a, b);
9783        assert_eq_m512d(r, _mm512_setzero_pd());
9784        let r = _mm512_maskz_permutevar_pd(0b00001111, a, b);
9785        let e = _mm512_set_pd(0., 0., 0., 0., 5., 5., 7., 7.);
9786        assert_eq_m512d(r, e);
9787    }
9788
9789    #[simd_test(enable = "avx512f,avx512vl")]
9790    unsafe fn test_mm256_mask_permutevar_pd() {
9791        let a = _mm256_set_pd(0., 1., 2., 3.);
9792        let b = _mm256_set1_epi64x(0b1);
9793        let r = _mm256_mask_permutevar_pd(a, 0, a, b);
9794        assert_eq_m256d(r, a);
9795        let r = _mm256_mask_permutevar_pd(a, 0b00001111, a, b);
9796        let e = _mm256_set_pd(1., 1., 3., 3.);
9797        assert_eq_m256d(r, e);
9798    }
9799
9800    #[simd_test(enable = "avx512f,avx512vl")]
9801    unsafe fn test_mm256_maskz_permutevar_pd() {
9802        let a = _mm256_set_pd(0., 1., 2., 3.);
9803        let b = _mm256_set1_epi64x(0b1);
9804        let r = _mm256_maskz_permutevar_pd(0, a, b);
9805        assert_eq_m256d(r, _mm256_setzero_pd());
9806        let r = _mm256_maskz_permutevar_pd(0b00001111, a, b);
9807        let e = _mm256_set_pd(1., 1., 3., 3.);
9808        assert_eq_m256d(r, e);
9809    }
9810
9811    #[simd_test(enable = "avx512f,avx512vl")]
9812    unsafe fn test_mm_mask_permutevar_pd() {
9813        let a = _mm_set_pd(0., 1.);
9814        let b = _mm_set1_epi64x(0b1);
9815        let r = _mm_mask_permutevar_pd(a, 0, a, b);
9816        assert_eq_m128d(r, a);
9817        let r = _mm_mask_permutevar_pd(a, 0b00000011, a, b);
9818        let e = _mm_set_pd(1., 1.);
9819        assert_eq_m128d(r, e);
9820    }
9821
9822    #[simd_test(enable = "avx512f,avx512vl")]
9823    unsafe fn test_mm_maskz_permutevar_pd() {
9824        let a = _mm_set_pd(0., 1.);
9825        let b = _mm_set1_epi64x(0b1);
9826        let r = _mm_maskz_permutevar_pd(0, a, b);
9827        assert_eq_m128d(r, _mm_setzero_pd());
9828        let r = _mm_maskz_permutevar_pd(0b00000011, a, b);
9829        let e = _mm_set_pd(1., 1.);
9830        assert_eq_m128d(r, e);
9831    }
9832
9833    #[simd_test(enable = "avx512f")]
9834    unsafe fn test_mm512_permutexvar_epi64() {
9835        let idx = _mm512_set1_epi64(1);
9836        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9837        let r = _mm512_permutexvar_epi64(idx, a);
9838        let e = _mm512_set1_epi64(6);
9839        assert_eq_m512i(r, e);
9840    }
9841
9842    #[simd_test(enable = "avx512f")]
9843    unsafe fn test_mm512_mask_permutexvar_epi64() {
9844        let idx = _mm512_set1_epi64(1);
9845        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9846        let r = _mm512_mask_permutexvar_epi64(a, 0, idx, a);
9847        assert_eq_m512i(r, a);
9848        let r = _mm512_mask_permutexvar_epi64(a, 0b11111111, idx, a);
9849        let e = _mm512_set1_epi64(6);
9850        assert_eq_m512i(r, e);
9851    }
9852
9853    #[simd_test(enable = "avx512f")]
9854    unsafe fn test_mm512_maskz_permutexvar_epi64() {
9855        let idx = _mm512_set1_epi64(1);
9856        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9857        let r = _mm512_maskz_permutexvar_epi64(0, idx, a);
9858        assert_eq_m512i(r, _mm512_setzero_si512());
9859        let r = _mm512_maskz_permutexvar_epi64(0b00001111, idx, a);
9860        let e = _mm512_set_epi64(0, 0, 0, 0, 6, 6, 6, 6);
9861        assert_eq_m512i(r, e);
9862    }
9863
9864    #[simd_test(enable = "avx512f,avx512vl")]
9865    unsafe fn test_mm256_permutexvar_epi64() {
9866        let idx = _mm256_set1_epi64x(1);
9867        let a = _mm256_set_epi64x(0, 1, 2, 3);
9868        let r = _mm256_permutexvar_epi64(idx, a);
9869        let e = _mm256_set1_epi64x(2);
9870        assert_eq_m256i(r, e);
9871    }
9872
9873    #[simd_test(enable = "avx512f,avx512vl")]
9874    unsafe fn test_mm256_mask_permutexvar_epi64() {
9875        let idx = _mm256_set1_epi64x(1);
9876        let a = _mm256_set_epi64x(0, 1, 2, 3);
9877        let r = _mm256_mask_permutexvar_epi64(a, 0, idx, a);
9878        assert_eq_m256i(r, a);
9879        let r = _mm256_mask_permutexvar_epi64(a, 0b00001111, idx, a);
9880        let e = _mm256_set1_epi64x(2);
9881        assert_eq_m256i(r, e);
9882    }
9883
9884    #[simd_test(enable = "avx512f,avx512vl")]
9885    unsafe fn test_mm256_maskz_permutexvar_epi64() {
9886        let idx = _mm256_set1_epi64x(1);
9887        let a = _mm256_set_epi64x(0, 1, 2, 3);
9888        let r = _mm256_maskz_permutexvar_epi64(0, idx, a);
9889        assert_eq_m256i(r, _mm256_setzero_si256());
9890        let r = _mm256_maskz_permutexvar_epi64(0b00001111, idx, a);
9891        let e = _mm256_set1_epi64x(2);
9892        assert_eq_m256i(r, e);
9893    }
9894
9895    #[simd_test(enable = "avx512f")]
9896    unsafe fn test_mm512_permutexvar_pd() {
9897        let idx = _mm512_set1_epi64(1);
9898        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9899        let r = _mm512_permutexvar_pd(idx, a);
9900        let e = _mm512_set1_pd(6.);
9901        assert_eq_m512d(r, e);
9902    }
9903
9904    #[simd_test(enable = "avx512f")]
9905    unsafe fn test_mm512_mask_permutexvar_pd() {
9906        let idx = _mm512_set1_epi64(1);
9907        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9908        let r = _mm512_mask_permutexvar_pd(a, 0, idx, a);
9909        assert_eq_m512d(r, a);
9910        let r = _mm512_mask_permutexvar_pd(a, 0b11111111, idx, a);
9911        let e = _mm512_set1_pd(6.);
9912        assert_eq_m512d(r, e);
9913    }
9914
9915    #[simd_test(enable = "avx512f")]
9916    unsafe fn test_mm512_maskz_permutexvar_pd() {
9917        let idx = _mm512_set1_epi64(1);
9918        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9919        let r = _mm512_maskz_permutexvar_pd(0, idx, a);
9920        assert_eq_m512d(r, _mm512_setzero_pd());
9921        let r = _mm512_maskz_permutexvar_pd(0b00001111, idx, a);
9922        let e = _mm512_set_pd(0., 0., 0., 0., 6., 6., 6., 6.);
9923        assert_eq_m512d(r, e);
9924    }
9925
9926    #[simd_test(enable = "avx512f,avx512vl")]
9927    unsafe fn test_mm256_permutexvar_pd() {
9928        let idx = _mm256_set1_epi64x(1);
9929        let a = _mm256_set_pd(0., 1., 2., 3.);
9930        let r = _mm256_permutexvar_pd(idx, a);
9931        let e = _mm256_set1_pd(2.);
9932        assert_eq_m256d(r, e);
9933    }
9934
9935    #[simd_test(enable = "avx512f,avx512vl")]
9936    unsafe fn test_mm256_mask_permutexvar_pd() {
9937        let idx = _mm256_set1_epi64x(1);
9938        let a = _mm256_set_pd(0., 1., 2., 3.);
9939        let r = _mm256_mask_permutexvar_pd(a, 0, idx, a);
9940        assert_eq_m256d(r, a);
9941        let r = _mm256_mask_permutexvar_pd(a, 0b00001111, idx, a);
9942        let e = _mm256_set1_pd(2.);
9943        assert_eq_m256d(r, e);
9944    }
9945
9946    #[simd_test(enable = "avx512f,avx512vl")]
9947    unsafe fn test_mm256_maskz_permutexvar_pd() {
9948        let idx = _mm256_set1_epi64x(1);
9949        let a = _mm256_set_pd(0., 1., 2., 3.);
9950        let r = _mm256_maskz_permutexvar_pd(0, idx, a);
9951        assert_eq_m256d(r, _mm256_setzero_pd());
9952        let r = _mm256_maskz_permutexvar_pd(0b00001111, idx, a);
9953        let e = _mm256_set1_pd(2.);
9954        assert_eq_m256d(r, e);
9955    }
9956
9957    #[simd_test(enable = "avx512f")]
9958    unsafe fn test_mm512_permutex2var_epi64() {
9959        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9960        let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9961        let b = _mm512_set1_epi64(100);
9962        let r = _mm512_permutex2var_epi64(a, idx, b);
9963        let e = _mm512_set_epi64(6, 100, 5, 100, 4, 100, 3, 100);
9964        assert_eq_m512i(r, e);
9965    }
9966
9967    #[simd_test(enable = "avx512f")]
9968    unsafe fn test_mm512_mask_permutex2var_epi64() {
9969        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9970        let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9971        let b = _mm512_set1_epi64(100);
9972        let r = _mm512_mask_permutex2var_epi64(a, 0, idx, b);
9973        assert_eq_m512i(r, a);
9974        let r = _mm512_mask_permutex2var_epi64(a, 0b11111111, idx, b);
9975        let e = _mm512_set_epi64(6, 100, 5, 100, 4, 100, 3, 100);
9976        assert_eq_m512i(r, e);
9977    }
9978
9979    #[simd_test(enable = "avx512f")]
9980    unsafe fn test_mm512_maskz_permutex2var_epi64() {
9981        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9982        let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9983        let b = _mm512_set1_epi64(100);
9984        let r = _mm512_maskz_permutex2var_epi64(0, a, idx, b);
9985        assert_eq_m512i(r, _mm512_setzero_si512());
9986        let r = _mm512_maskz_permutex2var_epi64(0b00001111, a, idx, b);
9987        let e = _mm512_set_epi64(0, 0, 0, 0, 4, 100, 3, 100);
9988        assert_eq_m512i(r, e);
9989    }
9990
9991    #[simd_test(enable = "avx512f")]
9992    unsafe fn test_mm512_mask2_permutex2var_epi64() {
9993        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9994        let idx = _mm512_set_epi64(1000, 1 << 3, 2000, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9995        let b = _mm512_set1_epi64(100);
9996        let r = _mm512_mask2_permutex2var_epi64(a, idx, 0, b);
9997        assert_eq_m512i(r, idx);
9998        let r = _mm512_mask2_permutex2var_epi64(a, idx, 0b00001111, b);
9999        let e = _mm512_set_epi64(1000, 1 << 3, 2000, 1 << 3, 4, 100, 3, 100);
10000        assert_eq_m512i(r, e);
10001    }
10002
10003    #[simd_test(enable = "avx512f,avx512vl")]
10004    unsafe fn test_mm256_permutex2var_epi64() {
10005        let a = _mm256_set_epi64x(0, 1, 2, 3);
10006        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10007        let b = _mm256_set1_epi64x(100);
10008        let r = _mm256_permutex2var_epi64(a, idx, b);
10009        let e = _mm256_set_epi64x(2, 100, 1, 100);
10010        assert_eq_m256i(r, e);
10011    }
10012
10013    #[simd_test(enable = "avx512f,avx512vl")]
10014    unsafe fn test_mm256_mask_permutex2var_epi64() {
10015        let a = _mm256_set_epi64x(0, 1, 2, 3);
10016        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10017        let b = _mm256_set1_epi64x(100);
10018        let r = _mm256_mask_permutex2var_epi64(a, 0, idx, b);
10019        assert_eq_m256i(r, a);
10020        let r = _mm256_mask_permutex2var_epi64(a, 0b00001111, idx, b);
10021        let e = _mm256_set_epi64x(2, 100, 1, 100);
10022        assert_eq_m256i(r, e);
10023    }
10024
10025    #[simd_test(enable = "avx512f,avx512vl")]
10026    unsafe fn test_mm256_maskz_permutex2var_epi64() {
10027        let a = _mm256_set_epi64x(0, 1, 2, 3);
10028        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10029        let b = _mm256_set1_epi64x(100);
10030        let r = _mm256_maskz_permutex2var_epi64(0, a, idx, b);
10031        assert_eq_m256i(r, _mm256_setzero_si256());
10032        let r = _mm256_maskz_permutex2var_epi64(0b00001111, a, idx, b);
10033        let e = _mm256_set_epi64x(2, 100, 1, 100);
10034        assert_eq_m256i(r, e);
10035    }
10036
10037    #[simd_test(enable = "avx512f,avx512vl")]
10038    unsafe fn test_mm256_mask2_permutex2var_epi64() {
10039        let a = _mm256_set_epi64x(0, 1, 2, 3);
10040        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10041        let b = _mm256_set1_epi64x(100);
10042        let r = _mm256_mask2_permutex2var_epi64(a, idx, 0, b);
10043        assert_eq_m256i(r, idx);
10044        let r = _mm256_mask2_permutex2var_epi64(a, idx, 0b00001111, b);
10045        let e = _mm256_set_epi64x(2, 100, 1, 100);
10046        assert_eq_m256i(r, e);
10047    }
10048
10049    #[simd_test(enable = "avx512f,avx512vl")]
10050    unsafe fn test_mm_permutex2var_epi64() {
10051        let a = _mm_set_epi64x(0, 1);
10052        let idx = _mm_set_epi64x(1, 1 << 1);
10053        let b = _mm_set1_epi64x(100);
10054        let r = _mm_permutex2var_epi64(a, idx, b);
10055        let e = _mm_set_epi64x(0, 100);
10056        assert_eq_m128i(r, e);
10057    }
10058
10059    #[simd_test(enable = "avx512f,avx512vl")]
10060    unsafe fn test_mm_mask_permutex2var_epi64() {
10061        let a = _mm_set_epi64x(0, 1);
10062        let idx = _mm_set_epi64x(1, 1 << 1);
10063        let b = _mm_set1_epi64x(100);
10064        let r = _mm_mask_permutex2var_epi64(a, 0, idx, b);
10065        assert_eq_m128i(r, a);
10066        let r = _mm_mask_permutex2var_epi64(a, 0b00000011, idx, b);
10067        let e = _mm_set_epi64x(0, 100);
10068        assert_eq_m128i(r, e);
10069    }
10070
10071    #[simd_test(enable = "avx512f,avx512vl")]
10072    unsafe fn test_mm_maskz_permutex2var_epi64() {
10073        let a = _mm_set_epi64x(0, 1);
10074        let idx = _mm_set_epi64x(1, 1 << 1);
10075        let b = _mm_set1_epi64x(100);
10076        let r = _mm_maskz_permutex2var_epi64(0, a, idx, b);
10077        assert_eq_m128i(r, _mm_setzero_si128());
10078        let r = _mm_maskz_permutex2var_epi64(0b00000011, a, idx, b);
10079        let e = _mm_set_epi64x(0, 100);
10080        assert_eq_m128i(r, e);
10081    }
10082
10083    #[simd_test(enable = "avx512f,avx512vl")]
10084    unsafe fn test_mm_mask2_permutex2var_epi64() {
10085        let a = _mm_set_epi64x(0, 1);
10086        let idx = _mm_set_epi64x(1, 1 << 1);
10087        let b = _mm_set1_epi64x(100);
10088        let r = _mm_mask2_permutex2var_epi64(a, idx, 0, b);
10089        assert_eq_m128i(r, idx);
10090        let r = _mm_mask2_permutex2var_epi64(a, idx, 0b00000011, b);
10091        let e = _mm_set_epi64x(0, 100);
10092        assert_eq_m128i(r, e);
10093    }
10094
10095    #[simd_test(enable = "avx512f")]
10096    unsafe fn test_mm512_permutex2var_pd() {
10097        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10098        let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10099        let b = _mm512_set1_pd(100.);
10100        let r = _mm512_permutex2var_pd(a, idx, b);
10101        let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
10102        assert_eq_m512d(r, e);
10103    }
10104
10105    #[simd_test(enable = "avx512f")]
10106    unsafe fn test_mm512_mask_permutex2var_pd() {
10107        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10108        let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10109        let b = _mm512_set1_pd(100.);
10110        let r = _mm512_mask_permutex2var_pd(a, 0, idx, b);
10111        assert_eq_m512d(r, a);
10112        let r = _mm512_mask_permutex2var_pd(a, 0b11111111, idx, b);
10113        let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
10114        assert_eq_m512d(r, e);
10115    }
10116
10117    #[simd_test(enable = "avx512f")]
10118    unsafe fn test_mm512_maskz_permutex2var_pd() {
10119        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10120        let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10121        let b = _mm512_set1_pd(100.);
10122        let r = _mm512_maskz_permutex2var_pd(0, a, idx, b);
10123        assert_eq_m512d(r, _mm512_setzero_pd());
10124        let r = _mm512_maskz_permutex2var_pd(0b00001111, a, idx, b);
10125        let e = _mm512_set_pd(0., 0., 0., 0., 4., 100., 3., 100.);
10126        assert_eq_m512d(r, e);
10127    }
10128
10129    #[simd_test(enable = "avx512f")]
10130    unsafe fn test_mm512_mask2_permutex2var_pd() {
10131        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10132        let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10133        let b = _mm512_set1_pd(100.);
10134        let r = _mm512_mask2_permutex2var_pd(a, idx, 0, b);
10135        assert_eq_m512d(r, _mm512_castsi512_pd(idx));
10136        let r = _mm512_mask2_permutex2var_pd(a, idx, 0b11111111, b);
10137        let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
10138        assert_eq_m512d(r, e);
10139    }
10140
10141    #[simd_test(enable = "avx512f,avx512vl")]
10142    unsafe fn test_mm256_permutex2var_pd() {
10143        let a = _mm256_set_pd(0., 1., 2., 3.);
10144        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10145        let b = _mm256_set1_pd(100.);
10146        let r = _mm256_permutex2var_pd(a, idx, b);
10147        let e = _mm256_set_pd(2., 100., 1., 100.);
10148        assert_eq_m256d(r, e);
10149    }
10150
10151    #[simd_test(enable = "avx512f,avx512vl")]
10152    unsafe fn test_mm256_mask_permutex2var_pd() {
10153        let a = _mm256_set_pd(0., 1., 2., 3.);
10154        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10155        let b = _mm256_set1_pd(100.);
10156        let r = _mm256_mask_permutex2var_pd(a, 0, idx, b);
10157        assert_eq_m256d(r, a);
10158        let r = _mm256_mask_permutex2var_pd(a, 0b00001111, idx, b);
10159        let e = _mm256_set_pd(2., 100., 1., 100.);
10160        assert_eq_m256d(r, e);
10161    }
10162
10163    #[simd_test(enable = "avx512f,avx512vl")]
10164    unsafe fn test_mm256_maskz_permutex2var_pd() {
10165        let a = _mm256_set_pd(0., 1., 2., 3.);
10166        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10167        let b = _mm256_set1_pd(100.);
10168        let r = _mm256_maskz_permutex2var_pd(0, a, idx, b);
10169        assert_eq_m256d(r, _mm256_setzero_pd());
10170        let r = _mm256_maskz_permutex2var_pd(0b00001111, a, idx, b);
10171        let e = _mm256_set_pd(2., 100., 1., 100.);
10172        assert_eq_m256d(r, e);
10173    }
10174
10175    #[simd_test(enable = "avx512f,avx512vl")]
10176    unsafe fn test_mm256_mask2_permutex2var_pd() {
10177        let a = _mm256_set_pd(0., 1., 2., 3.);
10178        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10179        let b = _mm256_set1_pd(100.);
10180        let r = _mm256_mask2_permutex2var_pd(a, idx, 0, b);
10181        assert_eq_m256d(r, _mm256_castsi256_pd(idx));
10182        let r = _mm256_mask2_permutex2var_pd(a, idx, 0b00001111, b);
10183        let e = _mm256_set_pd(2., 100., 1., 100.);
10184        assert_eq_m256d(r, e);
10185    }
10186
10187    #[simd_test(enable = "avx512f,avx512vl")]
10188    unsafe fn test_mm_permutex2var_pd() {
10189        let a = _mm_set_pd(0., 1.);
10190        let idx = _mm_set_epi64x(1, 1 << 1);
10191        let b = _mm_set1_pd(100.);
10192        let r = _mm_permutex2var_pd(a, idx, b);
10193        let e = _mm_set_pd(0., 100.);
10194        assert_eq_m128d(r, e);
10195    }
10196
10197    #[simd_test(enable = "avx512f,avx512vl")]
10198    unsafe fn test_mm_mask_permutex2var_pd() {
10199        let a = _mm_set_pd(0., 1.);
10200        let idx = _mm_set_epi64x(1, 1 << 1);
10201        let b = _mm_set1_pd(100.);
10202        let r = _mm_mask_permutex2var_pd(a, 0, idx, b);
10203        assert_eq_m128d(r, a);
10204        let r = _mm_mask_permutex2var_pd(a, 0b00000011, idx, b);
10205        let e = _mm_set_pd(0., 100.);
10206        assert_eq_m128d(r, e);
10207    }
10208
10209    #[simd_test(enable = "avx512f,avx512vl")]
10210    unsafe fn test_mm_maskz_permutex2var_pd() {
10211        let a = _mm_set_pd(0., 1.);
10212        let idx = _mm_set_epi64x(1, 1 << 1);
10213        let b = _mm_set1_pd(100.);
10214        let r = _mm_maskz_permutex2var_pd(0, a, idx, b);
10215        assert_eq_m128d(r, _mm_setzero_pd());
10216        let r = _mm_maskz_permutex2var_pd(0b00000011, a, idx, b);
10217        let e = _mm_set_pd(0., 100.);
10218        assert_eq_m128d(r, e);
10219    }
10220
10221    #[simd_test(enable = "avx512f,avx512vl")]
10222    unsafe fn test_mm_mask2_permutex2var_pd() {
10223        let a = _mm_set_pd(0., 1.);
10224        let idx = _mm_set_epi64x(1, 1 << 1);
10225        let b = _mm_set1_pd(100.);
10226        let r = _mm_mask2_permutex2var_pd(a, idx, 0, b);
10227        assert_eq_m128d(r, _mm_castsi128_pd(idx));
10228        let r = _mm_mask2_permutex2var_pd(a, idx, 0b00000011, b);
10229        let e = _mm_set_pd(0., 100.);
10230        assert_eq_m128d(r, e);
10231    }
10232
10233    #[simd_test(enable = "avx512f,avx512vl")]
10234    unsafe fn test_mm256_mask_shuffle_pd() {
10235        let a = _mm256_set_pd(1., 4., 5., 8.);
10236        let b = _mm256_set_pd(2., 3., 6., 7.);
10237        let r = _mm256_mask_shuffle_pd::<0b11_11_11_11>(a, 0, a, b);
10238        assert_eq_m256d(r, a);
10239        let r = _mm256_mask_shuffle_pd::<0b11_11_11_11>(a, 0b00001111, a, b);
10240        let e = _mm256_set_pd(2., 1., 6., 5.);
10241        assert_eq_m256d(r, e);
10242    }
10243
10244    #[simd_test(enable = "avx512f,avx512vl")]
10245    unsafe fn test_mm256_maskz_shuffle_pd() {
10246        let a = _mm256_set_pd(1., 4., 5., 8.);
10247        let b = _mm256_set_pd(2., 3., 6., 7.);
10248        let r = _mm256_maskz_shuffle_pd::<0b11_11_11_11>(0, a, b);
10249        assert_eq_m256d(r, _mm256_setzero_pd());
10250        let r = _mm256_maskz_shuffle_pd::<0b11_11_11_11>(0b00001111, a, b);
10251        let e = _mm256_set_pd(2., 1., 6., 5.);
10252        assert_eq_m256d(r, e);
10253    }
10254
10255    #[simd_test(enable = "avx512f,avx512vl")]
10256    unsafe fn test_mm_mask_shuffle_pd() {
10257        let a = _mm_set_pd(1., 4.);
10258        let b = _mm_set_pd(2., 3.);
10259        let r = _mm_mask_shuffle_pd::<0b11_11_11_11>(a, 0, a, b);
10260        assert_eq_m128d(r, a);
10261        let r = _mm_mask_shuffle_pd::<0b11_11_11_11>(a, 0b00000011, a, b);
10262        let e = _mm_set_pd(2., 1.);
10263        assert_eq_m128d(r, e);
10264    }
10265
10266    #[simd_test(enable = "avx512f,avx512vl")]
10267    unsafe fn test_mm_maskz_shuffle_pd() {
10268        let a = _mm_set_pd(1., 4.);
10269        let b = _mm_set_pd(2., 3.);
10270        let r = _mm_maskz_shuffle_pd::<0b11_11_11_11>(0, a, b);
10271        assert_eq_m128d(r, _mm_setzero_pd());
10272        let r = _mm_maskz_shuffle_pd::<0b11_11_11_11>(0b00000011, a, b);
10273        let e = _mm_set_pd(2., 1.);
10274        assert_eq_m128d(r, e);
10275    }
10276
10277    #[simd_test(enable = "avx512f")]
10278    unsafe fn test_mm512_shuffle_i64x2() {
10279        let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
10280        let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
10281        let r = _mm512_shuffle_i64x2::<0b00_00_00_00>(a, b);
10282        let e = _mm512_setr_epi64(1, 4, 1, 4, 2, 3, 2, 3);
10283        assert_eq_m512i(r, e);
10284    }
10285
10286    #[simd_test(enable = "avx512f")]
10287    unsafe fn test_mm512_mask_shuffle_i64x2() {
10288        let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
10289        let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
10290        let r = _mm512_mask_shuffle_i64x2::<0b00_00_00_00>(a, 0, a, b);
10291        assert_eq_m512i(r, a);
10292        let r = _mm512_mask_shuffle_i64x2::<0b00_00_00_00>(a, 0b11111111, a, b);
10293        let e = _mm512_setr_epi64(1, 4, 1, 4, 2, 3, 2, 3);
10294        assert_eq_m512i(r, e);
10295    }
10296
10297    #[simd_test(enable = "avx512f")]
10298    unsafe fn test_mm512_maskz_shuffle_i64x2() {
10299        let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
10300        let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
10301        let r = _mm512_maskz_shuffle_i64x2::<0b00_00_00_00>(0, a, b);
10302        assert_eq_m512i(r, _mm512_setzero_si512());
10303        let r = _mm512_maskz_shuffle_i64x2::<0b00_00_00_00>(0b00001111, a, b);
10304        let e = _mm512_setr_epi64(1, 4, 1, 4, 0, 0, 0, 0);
10305        assert_eq_m512i(r, e);
10306    }
10307
10308    #[simd_test(enable = "avx512f,avx512vl")]
10309    unsafe fn test_mm256_shuffle_i64x2() {
10310        let a = _mm256_set_epi64x(1, 4, 5, 8);
10311        let b = _mm256_set_epi64x(2, 3, 6, 7);
10312        let r = _mm256_shuffle_i64x2::<0b00>(a, b);
10313        let e = _mm256_set_epi64x(6, 7, 5, 8);
10314        assert_eq_m256i(r, e);
10315    }
10316
10317    #[simd_test(enable = "avx512f,avx512vl")]
10318    unsafe fn test_mm256_mask_shuffle_i64x2() {
10319        let a = _mm256_set_epi64x(1, 4, 5, 8);
10320        let b = _mm256_set_epi64x(2, 3, 6, 7);
10321        let r = _mm256_mask_shuffle_i64x2::<0b00>(a, 0, a, b);
10322        assert_eq_m256i(r, a);
10323        let r = _mm256_mask_shuffle_i64x2::<0b00>(a, 0b00001111, a, b);
10324        let e = _mm256_set_epi64x(6, 7, 5, 8);
10325        assert_eq_m256i(r, e);
10326    }
10327
10328    #[simd_test(enable = "avx512f,avx512vl")]
10329    unsafe fn test_mm256_maskz_shuffle_i64x2() {
10330        let a = _mm256_set_epi64x(1, 4, 5, 8);
10331        let b = _mm256_set_epi64x(2, 3, 6, 7);
10332        let r = _mm256_maskz_shuffle_i64x2::<0b00>(0, a, b);
10333        assert_eq_m256i(r, _mm256_setzero_si256());
10334        let r = _mm256_maskz_shuffle_i64x2::<0b00>(0b00001111, a, b);
10335        let e = _mm256_set_epi64x(6, 7, 5, 8);
10336        assert_eq_m256i(r, e);
10337    }
10338
10339    #[simd_test(enable = "avx512f")]
10340    unsafe fn test_mm512_shuffle_f64x2() {
10341        let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
10342        let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
10343        let r = _mm512_shuffle_f64x2::<0b00_00_00_00>(a, b);
10344        let e = _mm512_setr_pd(1., 4., 1., 4., 2., 3., 2., 3.);
10345        assert_eq_m512d(r, e);
10346    }
10347
10348    #[simd_test(enable = "avx512f")]
10349    unsafe fn test_mm512_mask_shuffle_f64x2() {
10350        let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
10351        let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
10352        let r = _mm512_mask_shuffle_f64x2::<0b00_00_00_00>(a, 0, a, b);
10353        assert_eq_m512d(r, a);
10354        let r = _mm512_mask_shuffle_f64x2::<0b00_00_00_00>(a, 0b11111111, a, b);
10355        let e = _mm512_setr_pd(1., 4., 1., 4., 2., 3., 2., 3.);
10356        assert_eq_m512d(r, e);
10357    }
10358
10359    #[simd_test(enable = "avx512f")]
10360    unsafe fn test_mm512_maskz_shuffle_f64x2() {
10361        let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
10362        let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
10363        let r = _mm512_maskz_shuffle_f64x2::<0b00_00_00_00>(0, a, b);
10364        assert_eq_m512d(r, _mm512_setzero_pd());
10365        let r = _mm512_maskz_shuffle_f64x2::<0b00_00_00_00>(0b00001111, a, b);
10366        let e = _mm512_setr_pd(1., 4., 1., 4., 0., 0., 0., 0.);
10367        assert_eq_m512d(r, e);
10368    }
10369
10370    #[simd_test(enable = "avx512f,avx512vl")]
10371    unsafe fn test_mm256_shuffle_f64x2() {
10372        let a = _mm256_set_pd(1., 4., 5., 8.);
10373        let b = _mm256_set_pd(2., 3., 6., 7.);
10374        let r = _mm256_shuffle_f64x2::<0b00>(a, b);
10375        let e = _mm256_set_pd(6., 7., 5., 8.);
10376        assert_eq_m256d(r, e);
10377    }
10378
10379    #[simd_test(enable = "avx512f,avx512vl")]
10380    unsafe fn test_mm256_mask_shuffle_f64x2() {
10381        let a = _mm256_set_pd(1., 4., 5., 8.);
10382        let b = _mm256_set_pd(2., 3., 6., 7.);
10383        let r = _mm256_mask_shuffle_f64x2::<0b00>(a, 0, a, b);
10384        assert_eq_m256d(r, a);
10385        let r = _mm256_mask_shuffle_f64x2::<0b00>(a, 0b00001111, a, b);
10386        let e = _mm256_set_pd(6., 7., 5., 8.);
10387        assert_eq_m256d(r, e);
10388    }
10389
10390    #[simd_test(enable = "avx512f,avx512vl")]
10391    unsafe fn test_mm256_maskz_shuffle_f64x2() {
10392        let a = _mm256_set_pd(1., 4., 5., 8.);
10393        let b = _mm256_set_pd(2., 3., 6., 7.);
10394        let r = _mm256_maskz_shuffle_f64x2::<0b00>(0, a, b);
10395        assert_eq_m256d(r, _mm256_setzero_pd());
10396        let r = _mm256_maskz_shuffle_f64x2::<0b00>(0b00001111, a, b);
10397        let e = _mm256_set_pd(6., 7., 5., 8.);
10398        assert_eq_m256d(r, e);
10399    }
10400
10401    #[simd_test(enable = "avx512f")]
10402    unsafe fn test_mm512_movedup_pd() {
10403        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10404        let r = _mm512_movedup_pd(a);
10405        let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
10406        assert_eq_m512d(r, e);
10407    }
10408
10409    #[simd_test(enable = "avx512f")]
10410    unsafe fn test_mm512_mask_movedup_pd() {
10411        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10412        let r = _mm512_mask_movedup_pd(a, 0, a);
10413        assert_eq_m512d(r, a);
10414        let r = _mm512_mask_movedup_pd(a, 0b11111111, a);
10415        let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
10416        assert_eq_m512d(r, e);
10417    }
10418
10419    #[simd_test(enable = "avx512f")]
10420    unsafe fn test_mm512_maskz_movedup_pd() {
10421        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10422        let r = _mm512_maskz_movedup_pd(0, a);
10423        assert_eq_m512d(r, _mm512_setzero_pd());
10424        let r = _mm512_maskz_movedup_pd(0b00001111, a);
10425        let e = _mm512_setr_pd(1., 1., 3., 3., 0., 0., 0., 0.);
10426        assert_eq_m512d(r, e);
10427    }
10428
10429    #[simd_test(enable = "avx512f,avx512vl")]
10430    unsafe fn test_mm256_mask_movedup_pd() {
10431        let a = _mm256_set_pd(1., 2., 3., 4.);
10432        let r = _mm256_mask_movedup_pd(a, 0, a);
10433        assert_eq_m256d(r, a);
10434        let r = _mm256_mask_movedup_pd(a, 0b00001111, a);
10435        let e = _mm256_set_pd(2., 2., 4., 4.);
10436        assert_eq_m256d(r, e);
10437    }
10438
10439    #[simd_test(enable = "avx512f,avx512vl")]
10440    unsafe fn test_mm256_maskz_movedup_pd() {
10441        let a = _mm256_set_pd(1., 2., 3., 4.);
10442        let r = _mm256_maskz_movedup_pd(0, a);
10443        assert_eq_m256d(r, _mm256_setzero_pd());
10444        let r = _mm256_maskz_movedup_pd(0b00001111, a);
10445        let e = _mm256_set_pd(2., 2., 4., 4.);
10446        assert_eq_m256d(r, e);
10447    }
10448
10449    #[simd_test(enable = "avx512f,avx512vl")]
10450    unsafe fn test_mm_mask_movedup_pd() {
10451        let a = _mm_set_pd(1., 2.);
10452        let r = _mm_mask_movedup_pd(a, 0, a);
10453        assert_eq_m128d(r, a);
10454        let r = _mm_mask_movedup_pd(a, 0b00000011, a);
10455        let e = _mm_set_pd(2., 2.);
10456        assert_eq_m128d(r, e);
10457    }
10458
10459    #[simd_test(enable = "avx512f,avx512vl")]
10460    unsafe fn test_mm_maskz_movedup_pd() {
10461        let a = _mm_set_pd(1., 2.);
10462        let r = _mm_maskz_movedup_pd(0, a);
10463        assert_eq_m128d(r, _mm_setzero_pd());
10464        let r = _mm_maskz_movedup_pd(0b00000011, a);
10465        let e = _mm_set_pd(2., 2.);
10466        assert_eq_m128d(r, e);
10467    }
10468
10469    #[simd_test(enable = "avx512f")]
10470    unsafe fn test_mm512_inserti64x4() {
10471        let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10472        let b = _mm256_setr_epi64x(17, 18, 19, 20);
10473        let r = _mm512_inserti64x4::<1>(a, b);
10474        let e = _mm512_setr_epi64(1, 2, 3, 4, 17, 18, 19, 20);
10475        assert_eq_m512i(r, e);
10476    }
10477
10478    #[simd_test(enable = "avx512f")]
10479    unsafe fn test_mm512_mask_inserti64x4() {
10480        let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10481        let b = _mm256_setr_epi64x(17, 18, 19, 20);
10482        let r = _mm512_mask_inserti64x4::<1>(a, 0, a, b);
10483        assert_eq_m512i(r, a);
10484        let r = _mm512_mask_inserti64x4::<1>(a, 0b11111111, a, b);
10485        let e = _mm512_setr_epi64(1, 2, 3, 4, 17, 18, 19, 20);
10486        assert_eq_m512i(r, e);
10487    }
10488
10489    #[simd_test(enable = "avx512f")]
10490    unsafe fn test_mm512_maskz_inserti64x4() {
10491        let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10492        let b = _mm256_setr_epi64x(17, 18, 19, 20);
10493        let r = _mm512_maskz_inserti64x4::<1>(0, a, b);
10494        assert_eq_m512i(r, _mm512_setzero_si512());
10495        let r = _mm512_maskz_inserti64x4::<1>(0b00001111, a, b);
10496        let e = _mm512_setr_epi64(1, 2, 3, 4, 0, 0, 0, 0);
10497        assert_eq_m512i(r, e);
10498    }
10499
10500    #[simd_test(enable = "avx512f")]
10501    unsafe fn test_mm512_insertf64x4() {
10502        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10503        let b = _mm256_setr_pd(17., 18., 19., 20.);
10504        let r = _mm512_insertf64x4::<1>(a, b);
10505        let e = _mm512_setr_pd(1., 2., 3., 4., 17., 18., 19., 20.);
10506        assert_eq_m512d(r, e);
10507    }
10508
10509    #[simd_test(enable = "avx512f")]
10510    unsafe fn test_mm512_mask_insertf64x4() {
10511        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10512        let b = _mm256_setr_pd(17., 18., 19., 20.);
10513        let r = _mm512_mask_insertf64x4::<1>(a, 0, a, b);
10514        assert_eq_m512d(r, a);
10515        let r = _mm512_mask_insertf64x4::<1>(a, 0b11111111, a, b);
10516        let e = _mm512_setr_pd(1., 2., 3., 4., 17., 18., 19., 20.);
10517        assert_eq_m512d(r, e);
10518    }
10519
10520    #[simd_test(enable = "avx512f")]
10521    unsafe fn test_mm512_maskz_insertf64x4() {
10522        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10523        let b = _mm256_setr_pd(17., 18., 19., 20.);
10524        let r = _mm512_maskz_insertf64x4::<1>(0, a, b);
10525        assert_eq_m512d(r, _mm512_setzero_pd());
10526        let r = _mm512_maskz_insertf64x4::<1>(0b00001111, a, b);
10527        let e = _mm512_setr_pd(1., 2., 3., 4., 0., 0., 0., 0.);
10528        assert_eq_m512d(r, e);
10529    }
10530
10531    #[simd_test(enable = "avx512f")]
10532    unsafe fn test_mm512_castpd128_pd512() {
10533        let a = _mm_setr_pd(17., 18.);
10534        let r = _mm512_castpd128_pd512(a);
10535        assert_eq_m128d(_mm512_castpd512_pd128(r), a);
10536    }
10537
10538    #[simd_test(enable = "avx512f")]
10539    unsafe fn test_mm512_castpd256_pd512() {
10540        let a = _mm256_setr_pd(17., 18., 19., 20.);
10541        let r = _mm512_castpd256_pd512(a);
10542        assert_eq_m256d(_mm512_castpd512_pd256(r), a);
10543    }
10544
10545    #[simd_test(enable = "avx512f")]
10546    unsafe fn test_mm512_zextpd128_pd512() {
10547        let a = _mm_setr_pd(17., 18.);
10548        let r = _mm512_zextpd128_pd512(a);
10549        let e = _mm512_setr_pd(17., 18., 0., 0., 0., 0., 0., 0.);
10550        assert_eq_m512d(r, e);
10551    }
10552
10553    #[simd_test(enable = "avx512f")]
10554    unsafe fn test_mm512_zextpd256_pd512() {
10555        let a = _mm256_setr_pd(17., 18., 19., 20.);
10556        let r = _mm512_zextpd256_pd512(a);
10557        let e = _mm512_setr_pd(17., 18., 19., 20., 0., 0., 0., 0.);
10558        assert_eq_m512d(r, e);
10559    }
10560
10561    #[simd_test(enable = "avx512f")]
10562    unsafe fn test_mm512_castpd512_pd128() {
10563        let a = _mm512_setr_pd(17., 18., -1., -1., -1., -1., -1., -1.);
10564        let r = _mm512_castpd512_pd128(a);
10565        let e = _mm_setr_pd(17., 18.);
10566        assert_eq_m128d(r, e);
10567    }
10568
10569    #[simd_test(enable = "avx512f")]
10570    unsafe fn test_mm512_castpd512_pd256() {
10571        let a = _mm512_setr_pd(17., 18., 19., 20., -1., -1., -1., -1.);
10572        let r = _mm512_castpd512_pd256(a);
10573        let e = _mm256_setr_pd(17., 18., 19., 20.);
10574        assert_eq_m256d(r, e);
10575    }
10576
10577    #[simd_test(enable = "avx512f")]
10578    unsafe fn test_mm512_castpd_ps() {
10579        let a = _mm512_set1_pd(1.);
10580        let r = _mm512_castpd_ps(a);
10581        let e = _mm512_set_ps(
10582            1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0,
10583            1.875, 0.0,
10584        );
10585        assert_eq_m512(r, e);
10586    }
10587
10588    #[simd_test(enable = "avx512f")]
10589    unsafe fn test_mm512_castpd_si512() {
10590        let a = _mm512_set1_pd(1.);
10591        let r = _mm512_castpd_si512(a);
10592        let e = _mm512_set_epi32(
10593            1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248,
10594            0, 1072693248, 0, 1072693248, 0,
10595        );
10596        assert_eq_m512i(r, e);
10597    }
10598
10599    #[simd_test(enable = "avx512f")]
10600    unsafe fn test_mm512_castsi128_si512() {
10601        let a = _mm_setr_epi64x(17, 18);
10602        let r = _mm512_castsi128_si512(a);
10603        assert_eq_m128i(_mm512_castsi512_si128(r), a);
10604    }
10605
10606    #[simd_test(enable = "avx512f")]
10607    unsafe fn test_mm512_castsi256_si512() {
10608        let a = _mm256_setr_epi64x(17, 18, 19, 20);
10609        let r = _mm512_castsi256_si512(a);
10610        assert_eq_m256i(_mm512_castsi512_si256(r), a);
10611    }
10612
10613    #[simd_test(enable = "avx512f")]
10614    unsafe fn test_mm512_zextsi128_si512() {
10615        let a = _mm_setr_epi64x(17, 18);
10616        let r = _mm512_zextsi128_si512(a);
10617        let e = _mm512_setr_epi64(17, 18, 0, 0, 0, 0, 0, 0);
10618        assert_eq_m512i(r, e);
10619    }
10620
10621    #[simd_test(enable = "avx512f")]
10622    unsafe fn test_mm512_zextsi256_si512() {
10623        let a = _mm256_setr_epi64x(17, 18, 19, 20);
10624        let r = _mm512_zextsi256_si512(a);
10625        let e = _mm512_setr_epi64(17, 18, 19, 20, 0, 0, 0, 0);
10626        assert_eq_m512i(r, e);
10627    }
10628
10629    #[simd_test(enable = "avx512f")]
10630    unsafe fn test_mm512_castsi512_si128() {
10631        let a = _mm512_setr_epi64(17, 18, -1, -1, -1, -1, -1, -1);
10632        let r = _mm512_castsi512_si128(a);
10633        let e = _mm_setr_epi64x(17, 18);
10634        assert_eq_m128i(r, e);
10635    }
10636
10637    #[simd_test(enable = "avx512f")]
10638    unsafe fn test_mm512_castsi512_si256() {
10639        let a = _mm512_setr_epi64(17, 18, 19, 20, -1, -1, -1, -1);
10640        let r = _mm512_castsi512_si256(a);
10641        let e = _mm256_setr_epi64x(17, 18, 19, 20);
10642        assert_eq_m256i(r, e);
10643    }
10644
10645    #[simd_test(enable = "avx512f")]
10646    unsafe fn test_mm512_castsi512_ps() {
10647        let a = _mm512_set1_epi64(1 << 62);
10648        let r = _mm512_castsi512_ps(a);
10649        let e = _mm512_set_ps(
10650            2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0.,
10651        );
10652        assert_eq_m512(r, e);
10653    }
10654
10655    #[simd_test(enable = "avx512f")]
10656    unsafe fn test_mm512_castsi512_pd() {
10657        let a = _mm512_set1_epi64(1 << 62);
10658        let r = _mm512_castsi512_pd(a);
10659        let e = _mm512_set_pd(2., 2., 2., 2., 2., 2., 2., 2.);
10660        assert_eq_m512d(r, e);
10661    }
10662
10663    #[simd_test(enable = "avx512f")]
10664    unsafe fn test_mm512_broadcastq_epi64() {
10665        let a = _mm_setr_epi64x(17, 18);
10666        let r = _mm512_broadcastq_epi64(a);
10667        let e = _mm512_set1_epi64(17);
10668        assert_eq_m512i(r, e);
10669    }
10670
10671    #[simd_test(enable = "avx512f")]
10672    unsafe fn test_mm512_mask_broadcastq_epi64() {
10673        let src = _mm512_set1_epi64(18);
10674        let a = _mm_setr_epi64x(17, 18);
10675        let r = _mm512_mask_broadcastq_epi64(src, 0, a);
10676        assert_eq_m512i(r, src);
10677        let r = _mm512_mask_broadcastq_epi64(src, 0b11111111, a);
10678        let e = _mm512_set1_epi64(17);
10679        assert_eq_m512i(r, e);
10680    }
10681
10682    #[simd_test(enable = "avx512f")]
10683    unsafe fn test_mm512_maskz_broadcastq_epi64() {
10684        let a = _mm_setr_epi64x(17, 18);
10685        let r = _mm512_maskz_broadcastq_epi64(0, a);
10686        assert_eq_m512i(r, _mm512_setzero_si512());
10687        let r = _mm512_maskz_broadcastq_epi64(0b00001111, a);
10688        let e = _mm512_set_epi64(0, 0, 0, 0, 17, 17, 17, 17);
10689        assert_eq_m512i(r, e);
10690    }
10691
10692    #[simd_test(enable = "avx512f,avx512vl")]
10693    unsafe fn test_mm256_mask_broadcastq_epi64() {
10694        let src = _mm256_set1_epi64x(18);
10695        let a = _mm_set_epi64x(17, 18);
10696        let r = _mm256_mask_broadcastq_epi64(src, 0, a);
10697        assert_eq_m256i(r, src);
10698        let r = _mm256_mask_broadcastq_epi64(src, 0b00001111, a);
10699        let e = _mm256_set1_epi64x(18);
10700        assert_eq_m256i(r, e);
10701    }
10702
10703    #[simd_test(enable = "avx512f,avx512vl")]
10704    unsafe fn test_mm256_maskz_broadcastq_epi64() {
10705        let a = _mm_set_epi64x(17, 18);
10706        let r = _mm256_maskz_broadcastq_epi64(0, a);
10707        assert_eq_m256i(r, _mm256_setzero_si256());
10708        let r = _mm256_maskz_broadcastq_epi64(0b00001111, a);
10709        let e = _mm256_set1_epi64x(18);
10710        assert_eq_m256i(r, e);
10711    }
10712
10713    #[simd_test(enable = "avx512f,avx512vl")]
10714    unsafe fn test_mm_mask_broadcastq_epi64() {
10715        let src = _mm_set1_epi64x(18);
10716        let a = _mm_set_epi64x(17, 18);
10717        let r = _mm_mask_broadcastq_epi64(src, 0, a);
10718        assert_eq_m128i(r, src);
10719        let r = _mm_mask_broadcastq_epi64(src, 0b00000011, a);
10720        let e = _mm_set1_epi64x(18);
10721        assert_eq_m128i(r, e);
10722    }
10723
10724    #[simd_test(enable = "avx512f,avx512vl")]
10725    unsafe fn test_mm_maskz_broadcastq_epi64() {
10726        let a = _mm_set_epi64x(17, 18);
10727        let r = _mm_maskz_broadcastq_epi64(0, a);
10728        assert_eq_m128i(r, _mm_setzero_si128());
10729        let r = _mm_maskz_broadcastq_epi64(0b00000011, a);
10730        let e = _mm_set1_epi64x(18);
10731        assert_eq_m128i(r, e);
10732    }
10733
10734    #[simd_test(enable = "avx512f")]
10735    unsafe fn test_mm512_broadcastsd_pd() {
10736        let a = _mm_set_pd(17., 18.);
10737        let r = _mm512_broadcastsd_pd(a);
10738        let e = _mm512_set1_pd(18.);
10739        assert_eq_m512d(r, e);
10740    }
10741
10742    #[simd_test(enable = "avx512f")]
10743    unsafe fn test_mm512_mask_broadcastsd_pd() {
10744        let src = _mm512_set1_pd(18.);
10745        let a = _mm_set_pd(17., 18.);
10746        let r = _mm512_mask_broadcastsd_pd(src, 0, a);
10747        assert_eq_m512d(r, src);
10748        let r = _mm512_mask_broadcastsd_pd(src, 0b11111111, a);
10749        let e = _mm512_set1_pd(18.);
10750        assert_eq_m512d(r, e);
10751    }
10752
10753    #[simd_test(enable = "avx512f")]
10754    unsafe fn test_mm512_maskz_broadcastsd_pd() {
10755        let a = _mm_set_pd(17., 18.);
10756        let r = _mm512_maskz_broadcastsd_pd(0, a);
10757        assert_eq_m512d(r, _mm512_setzero_pd());
10758        let r = _mm512_maskz_broadcastsd_pd(0b00001111, a);
10759        let e = _mm512_set_pd(0., 0., 0., 0., 18., 18., 18., 18.);
10760        assert_eq_m512d(r, e);
10761    }
10762
10763    #[simd_test(enable = "avx512f,avx512vl")]
10764    unsafe fn test_mm256_mask_broadcastsd_pd() {
10765        let src = _mm256_set1_pd(18.);
10766        let a = _mm_set_pd(17., 18.);
10767        let r = _mm256_mask_broadcastsd_pd(src, 0, a);
10768        assert_eq_m256d(r, src);
10769        let r = _mm256_mask_broadcastsd_pd(src, 0b00001111, a);
10770        let e = _mm256_set1_pd(18.);
10771        assert_eq_m256d(r, e);
10772    }
10773
10774    #[simd_test(enable = "avx512f,avx512vl")]
10775    unsafe fn test_mm256_maskz_broadcastsd_pd() {
10776        let a = _mm_set_pd(17., 18.);
10777        let r = _mm256_maskz_broadcastsd_pd(0, a);
10778        assert_eq_m256d(r, _mm256_setzero_pd());
10779        let r = _mm256_maskz_broadcastsd_pd(0b00001111, a);
10780        let e = _mm256_set1_pd(18.);
10781        assert_eq_m256d(r, e);
10782    }
10783
10784    #[simd_test(enable = "avx512f")]
10785    unsafe fn test_mm512_broadcast_i64x4() {
10786        let a = _mm256_set_epi64x(17, 18, 19, 20);
10787        let r = _mm512_broadcast_i64x4(a);
10788        let e = _mm512_set_epi64(17, 18, 19, 20, 17, 18, 19, 20);
10789        assert_eq_m512i(r, e);
10790    }
10791
10792    #[simd_test(enable = "avx512f")]
10793    unsafe fn test_mm512_mask_broadcast_i64x4() {
10794        let src = _mm512_set1_epi64(18);
10795        let a = _mm256_set_epi64x(17, 18, 19, 20);
10796        let r = _mm512_mask_broadcast_i64x4(src, 0, a);
10797        assert_eq_m512i(r, src);
10798        let r = _mm512_mask_broadcast_i64x4(src, 0b11111111, a);
10799        let e = _mm512_set_epi64(17, 18, 19, 20, 17, 18, 19, 20);
10800        assert_eq_m512i(r, e);
10801    }
10802
10803    #[simd_test(enable = "avx512f")]
10804    unsafe fn test_mm512_maskz_broadcast_i64x4() {
10805        let a = _mm256_set_epi64x(17, 18, 19, 20);
10806        let r = _mm512_maskz_broadcast_i64x4(0, a);
10807        assert_eq_m512i(r, _mm512_setzero_si512());
10808        let r = _mm512_maskz_broadcast_i64x4(0b00001111, a);
10809        let e = _mm512_set_epi64(0, 0, 0, 0, 17, 18, 19, 20);
10810        assert_eq_m512i(r, e);
10811    }
10812
10813    #[simd_test(enable = "avx512f")]
10814    unsafe fn test_mm512_broadcast_f64x4() {
10815        let a = _mm256_set_pd(17., 18., 19., 20.);
10816        let r = _mm512_broadcast_f64x4(a);
10817        let e = _mm512_set_pd(17., 18., 19., 20., 17., 18., 19., 20.);
10818        assert_eq_m512d(r, e);
10819    }
10820
10821    #[simd_test(enable = "avx512f")]
10822    unsafe fn test_mm512_mask_broadcast_f64x4() {
10823        let src = _mm512_set1_pd(18.);
10824        let a = _mm256_set_pd(17., 18., 19., 20.);
10825        let r = _mm512_mask_broadcast_f64x4(src, 0, a);
10826        assert_eq_m512d(r, src);
10827        let r = _mm512_mask_broadcast_f64x4(src, 0b11111111, a);
10828        let e = _mm512_set_pd(17., 18., 19., 20., 17., 18., 19., 20.);
10829        assert_eq_m512d(r, e);
10830    }
10831
10832    #[simd_test(enable = "avx512f")]
10833    unsafe fn test_mm512_maskz_broadcast_f64x4() {
10834        let a = _mm256_set_pd(17., 18., 19., 20.);
10835        let r = _mm512_maskz_broadcast_f64x4(0, a);
10836        assert_eq_m512d(r, _mm512_setzero_pd());
10837        let r = _mm512_maskz_broadcast_f64x4(0b00001111, a);
10838        let e = _mm512_set_pd(0., 0., 0., 0., 17., 18., 19., 20.);
10839        assert_eq_m512d(r, e);
10840    }
10841
10842    #[simd_test(enable = "avx512f")]
10843    unsafe fn test_mm512_mask_blend_epi64() {
10844        let a = _mm512_set1_epi64(1);
10845        let b = _mm512_set1_epi64(2);
10846        let r = _mm512_mask_blend_epi64(0b11110000, a, b);
10847        let e = _mm512_set_epi64(2, 2, 2, 2, 1, 1, 1, 1);
10848        assert_eq_m512i(r, e);
10849    }
10850
10851    #[simd_test(enable = "avx512f,avx512vl")]
10852    unsafe fn test_mm256_mask_blend_epi64() {
10853        let a = _mm256_set1_epi64x(1);
10854        let b = _mm256_set1_epi64x(2);
10855        let r = _mm256_mask_blend_epi64(0b00001111, a, b);
10856        let e = _mm256_set1_epi64x(2);
10857        assert_eq_m256i(r, e);
10858    }
10859
10860    #[simd_test(enable = "avx512f,avx512vl")]
10861    unsafe fn test_mm_mask_blend_epi64() {
10862        let a = _mm_set1_epi64x(1);
10863        let b = _mm_set1_epi64x(2);
10864        let r = _mm_mask_blend_epi64(0b00000011, a, b);
10865        let e = _mm_set1_epi64x(2);
10866        assert_eq_m128i(r, e);
10867    }
10868
10869    #[simd_test(enable = "avx512f")]
10870    unsafe fn test_mm512_mask_blend_pd() {
10871        let a = _mm512_set1_pd(1.);
10872        let b = _mm512_set1_pd(2.);
10873        let r = _mm512_mask_blend_pd(0b11110000, a, b);
10874        let e = _mm512_set_pd(2., 2., 2., 2., 1., 1., 1., 1.);
10875        assert_eq_m512d(r, e);
10876    }
10877
10878    #[simd_test(enable = "avx512f,avx512vl")]
10879    unsafe fn test_mm256_mask_blend_pd() {
10880        let a = _mm256_set1_pd(1.);
10881        let b = _mm256_set1_pd(2.);
10882        let r = _mm256_mask_blend_pd(0b00001111, a, b);
10883        let e = _mm256_set1_pd(2.);
10884        assert_eq_m256d(r, e);
10885    }
10886
10887    #[simd_test(enable = "avx512f,avx512vl")]
10888    unsafe fn test_mm_mask_blend_pd() {
10889        let a = _mm_set1_pd(1.);
10890        let b = _mm_set1_pd(2.);
10891        let r = _mm_mask_blend_pd(0b00000011, a, b);
10892        let e = _mm_set1_pd(2.);
10893        assert_eq_m128d(r, e);
10894    }
10895
10896    #[simd_test(enable = "avx512f")]
10897    unsafe fn test_mm512_unpackhi_epi64() {
10898        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10899        let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10900        let r = _mm512_unpackhi_epi64(a, b);
10901        let e = _mm512_set_epi64(17, 1, 19, 3, 21, 5, 23, 7);
10902        assert_eq_m512i(r, e);
10903    }
10904
10905    #[simd_test(enable = "avx512f")]
10906    unsafe fn test_mm512_mask_unpackhi_epi64() {
10907        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10908        let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10909        let r = _mm512_mask_unpackhi_epi64(a, 0, a, b);
10910        assert_eq_m512i(r, a);
10911        let r = _mm512_mask_unpackhi_epi64(a, 0b11111111, a, b);
10912        let e = _mm512_set_epi64(17, 1, 19, 3, 21, 5, 23, 7);
10913        assert_eq_m512i(r, e);
10914    }
10915
10916    #[simd_test(enable = "avx512f")]
10917    unsafe fn test_mm512_maskz_unpackhi_epi64() {
10918        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10919        let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10920        let r = _mm512_maskz_unpackhi_epi64(0, a, b);
10921        assert_eq_m512i(r, _mm512_setzero_si512());
10922        let r = _mm512_maskz_unpackhi_epi64(0b00001111, a, b);
10923        let e = _mm512_set_epi64(0, 0, 0, 0, 21, 5, 23, 7);
10924        assert_eq_m512i(r, e);
10925    }
10926
10927    #[simd_test(enable = "avx512f,avx512vl")]
10928    unsafe fn test_mm256_mask_unpackhi_epi64() {
10929        let a = _mm256_set_epi64x(1, 2, 3, 4);
10930        let b = _mm256_set_epi64x(17, 18, 19, 20);
10931        let r = _mm256_mask_unpackhi_epi64(a, 0, a, b);
10932        assert_eq_m256i(r, a);
10933        let r = _mm256_mask_unpackhi_epi64(a, 0b00001111, a, b);
10934        let e = _mm256_set_epi64x(17, 1, 19, 3);
10935        assert_eq_m256i(r, e);
10936    }
10937
10938    #[simd_test(enable = "avx512f,avx512vl")]
10939    unsafe fn test_mm256_maskz_unpackhi_epi64() {
10940        let a = _mm256_set_epi64x(1, 2, 3, 4);
10941        let b = _mm256_set_epi64x(17, 18, 19, 20);
10942        let r = _mm256_maskz_unpackhi_epi64(0, a, b);
10943        assert_eq_m256i(r, _mm256_setzero_si256());
10944        let r = _mm256_maskz_unpackhi_epi64(0b00001111, a, b);
10945        let e = _mm256_set_epi64x(17, 1, 19, 3);
10946        assert_eq_m256i(r, e);
10947    }
10948
10949    #[simd_test(enable = "avx512f,avx512vl")]
10950    unsafe fn test_mm_mask_unpackhi_epi64() {
10951        let a = _mm_set_epi64x(1, 2);
10952        let b = _mm_set_epi64x(17, 18);
10953        let r = _mm_mask_unpackhi_epi64(a, 0, a, b);
10954        assert_eq_m128i(r, a);
10955        let r = _mm_mask_unpackhi_epi64(a, 0b00000011, a, b);
10956        let e = _mm_set_epi64x(17, 1);
10957        assert_eq_m128i(r, e);
10958    }
10959
10960    #[simd_test(enable = "avx512f,avx512vl")]
10961    unsafe fn test_mm_maskz_unpackhi_epi64() {
10962        let a = _mm_set_epi64x(1, 2);
10963        let b = _mm_set_epi64x(17, 18);
10964        let r = _mm_maskz_unpackhi_epi64(0, a, b);
10965        assert_eq_m128i(r, _mm_setzero_si128());
10966        let r = _mm_maskz_unpackhi_epi64(0b00000011, a, b);
10967        let e = _mm_set_epi64x(17, 1);
10968        assert_eq_m128i(r, e);
10969    }
10970
10971    #[simd_test(enable = "avx512f")]
10972    unsafe fn test_mm512_unpackhi_pd() {
10973        let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10974        let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10975        let r = _mm512_unpackhi_pd(a, b);
10976        let e = _mm512_set_pd(17., 1., 19., 3., 21., 5., 23., 7.);
10977        assert_eq_m512d(r, e);
10978    }
10979
10980    #[simd_test(enable = "avx512f")]
10981    unsafe fn test_mm512_mask_unpackhi_pd() {
10982        let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10983        let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10984        let r = _mm512_mask_unpackhi_pd(a, 0, a, b);
10985        assert_eq_m512d(r, a);
10986        let r = _mm512_mask_unpackhi_pd(a, 0b11111111, a, b);
10987        let e = _mm512_set_pd(17., 1., 19., 3., 21., 5., 23., 7.);
10988        assert_eq_m512d(r, e);
10989    }
10990
10991    #[simd_test(enable = "avx512f")]
10992    unsafe fn test_mm512_maskz_unpackhi_pd() {
10993        let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10994        let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10995        let r = _mm512_maskz_unpackhi_pd(0, a, b);
10996        assert_eq_m512d(r, _mm512_setzero_pd());
10997        let r = _mm512_maskz_unpackhi_pd(0b00001111, a, b);
10998        let e = _mm512_set_pd(0., 0., 0., 0., 21., 5., 23., 7.);
10999        assert_eq_m512d(r, e);
11000    }
11001
11002    #[simd_test(enable = "avx512f,avx512vl")]
11003    unsafe fn test_mm256_mask_unpackhi_pd() {
11004        let a = _mm256_set_pd(1., 2., 3., 4.);
11005        let b = _mm256_set_pd(17., 18., 19., 20.);
11006        let r = _mm256_mask_unpackhi_pd(a, 0, a, b);
11007        assert_eq_m256d(r, a);
11008        let r = _mm256_mask_unpackhi_pd(a, 0b00001111, a, b);
11009        let e = _mm256_set_pd(17., 1., 19., 3.);
11010        assert_eq_m256d(r, e);
11011    }
11012
11013    #[simd_test(enable = "avx512f,avx512vl")]
11014    unsafe fn test_mm256_maskz_unpackhi_pd() {
11015        let a = _mm256_set_pd(1., 2., 3., 4.);
11016        let b = _mm256_set_pd(17., 18., 19., 20.);
11017        let r = _mm256_maskz_unpackhi_pd(0, a, b);
11018        assert_eq_m256d(r, _mm256_setzero_pd());
11019        let r = _mm256_maskz_unpackhi_pd(0b00001111, a, b);
11020        let e = _mm256_set_pd(17., 1., 19., 3.);
11021        assert_eq_m256d(r, e);
11022    }
11023
11024    #[simd_test(enable = "avx512f,avx512vl")]
11025    unsafe fn test_mm_mask_unpackhi_pd() {
11026        let a = _mm_set_pd(1., 2.);
11027        let b = _mm_set_pd(17., 18.);
11028        let r = _mm_mask_unpackhi_pd(a, 0, a, b);
11029        assert_eq_m128d(r, a);
11030        let r = _mm_mask_unpackhi_pd(a, 0b00000011, a, b);
11031        let e = _mm_set_pd(17., 1.);
11032        assert_eq_m128d(r, e);
11033    }
11034
11035    #[simd_test(enable = "avx512f,avx512vl")]
11036    unsafe fn test_mm_maskz_unpackhi_pd() {
11037        let a = _mm_set_pd(1., 2.);
11038        let b = _mm_set_pd(17., 18.);
11039        let r = _mm_maskz_unpackhi_pd(0, a, b);
11040        assert_eq_m128d(r, _mm_setzero_pd());
11041        let r = _mm_maskz_unpackhi_pd(0b00000011, a, b);
11042        let e = _mm_set_pd(17., 1.);
11043        assert_eq_m128d(r, e);
11044    }
11045
11046    #[simd_test(enable = "avx512f")]
11047    unsafe fn test_mm512_unpacklo_epi64() {
11048        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11049        let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
11050        let r = _mm512_unpacklo_epi64(a, b);
11051        let e = _mm512_set_epi64(18, 2, 20, 4, 22, 6, 24, 8);
11052        assert_eq_m512i(r, e);
11053    }
11054
11055    #[simd_test(enable = "avx512f")]
11056    unsafe fn test_mm512_mask_unpacklo_epi64() {
11057        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11058        let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
11059        let r = _mm512_mask_unpacklo_epi64(a, 0, a, b);
11060        assert_eq_m512i(r, a);
11061        let r = _mm512_mask_unpacklo_epi64(a, 0b11111111, a, b);
11062        let e = _mm512_set_epi64(18, 2, 20, 4, 22, 6, 24, 8);
11063        assert_eq_m512i(r, e);
11064    }
11065
11066    #[simd_test(enable = "avx512f")]
11067    unsafe fn test_mm512_maskz_unpacklo_epi64() {
11068        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11069        let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
11070        let r = _mm512_maskz_unpacklo_epi64(0, a, b);
11071        assert_eq_m512i(r, _mm512_setzero_si512());
11072        let r = _mm512_maskz_unpacklo_epi64(0b00001111, a, b);
11073        let e = _mm512_set_epi64(0, 0, 0, 0, 22, 6, 24, 8);
11074        assert_eq_m512i(r, e);
11075    }
11076
11077    #[simd_test(enable = "avx512f,avx512vl")]
11078    unsafe fn test_mm256_mask_unpacklo_epi64() {
11079        let a = _mm256_set_epi64x(1, 2, 3, 4);
11080        let b = _mm256_set_epi64x(17, 18, 19, 20);
11081        let r = _mm256_mask_unpacklo_epi64(a, 0, a, b);
11082        assert_eq_m256i(r, a);
11083        let r = _mm256_mask_unpacklo_epi64(a, 0b00001111, a, b);
11084        let e = _mm256_set_epi64x(18, 2, 20, 4);
11085        assert_eq_m256i(r, e);
11086    }
11087
11088    #[simd_test(enable = "avx512f,avx512vl")]
11089    unsafe fn test_mm256_maskz_unpacklo_epi64() {
11090        let a = _mm256_set_epi64x(1, 2, 3, 4);
11091        let b = _mm256_set_epi64x(17, 18, 19, 20);
11092        let r = _mm256_maskz_unpacklo_epi64(0, a, b);
11093        assert_eq_m256i(r, _mm256_setzero_si256());
11094        let r = _mm256_maskz_unpacklo_epi64(0b00001111, a, b);
11095        let e = _mm256_set_epi64x(18, 2, 20, 4);
11096        assert_eq_m256i(r, e);
11097    }
11098
11099    #[simd_test(enable = "avx512f,avx512vl")]
11100    unsafe fn test_mm_mask_unpacklo_epi64() {
11101        let a = _mm_set_epi64x(1, 2);
11102        let b = _mm_set_epi64x(17, 18);
11103        let r = _mm_mask_unpacklo_epi64(a, 0, a, b);
11104        assert_eq_m128i(r, a);
11105        let r = _mm_mask_unpacklo_epi64(a, 0b00000011, a, b);
11106        let e = _mm_set_epi64x(18, 2);
11107        assert_eq_m128i(r, e);
11108    }
11109
11110    #[simd_test(enable = "avx512f,avx512vl")]
11111    unsafe fn test_mm_maskz_unpacklo_epi64() {
11112        let a = _mm_set_epi64x(1, 2);
11113        let b = _mm_set_epi64x(17, 18);
11114        let r = _mm_maskz_unpacklo_epi64(0, a, b);
11115        assert_eq_m128i(r, _mm_setzero_si128());
11116        let r = _mm_maskz_unpacklo_epi64(0b00000011, a, b);
11117        let e = _mm_set_epi64x(18, 2);
11118        assert_eq_m128i(r, e);
11119    }
11120
11121    #[simd_test(enable = "avx512f")]
11122    unsafe fn test_mm512_unpacklo_pd() {
11123        let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11124        let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
11125        let r = _mm512_unpacklo_pd(a, b);
11126        let e = _mm512_set_pd(18., 2., 20., 4., 22., 6., 24., 8.);
11127        assert_eq_m512d(r, e);
11128    }
11129
11130    #[simd_test(enable = "avx512f")]
11131    unsafe fn test_mm512_mask_unpacklo_pd() {
11132        let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11133        let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
11134        let r = _mm512_mask_unpacklo_pd(a, 0, a, b);
11135        assert_eq_m512d(r, a);
11136        let r = _mm512_mask_unpacklo_pd(a, 0b11111111, a, b);
11137        let e = _mm512_set_pd(18., 2., 20., 4., 22., 6., 24., 8.);
11138        assert_eq_m512d(r, e);
11139    }
11140
11141    #[simd_test(enable = "avx512f")]
11142    unsafe fn test_mm512_maskz_unpacklo_pd() {
11143        let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11144        let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
11145        let r = _mm512_maskz_unpacklo_pd(0, a, b);
11146        assert_eq_m512d(r, _mm512_setzero_pd());
11147        let r = _mm512_maskz_unpacklo_pd(0b00001111, a, b);
11148        let e = _mm512_set_pd(0., 0., 0., 0., 22., 6., 24., 8.);
11149        assert_eq_m512d(r, e);
11150    }
11151
11152    #[simd_test(enable = "avx512f,avx512vl")]
11153    unsafe fn test_mm256_mask_unpacklo_pd() {
11154        let a = _mm256_set_pd(1., 2., 3., 4.);
11155        let b = _mm256_set_pd(17., 18., 19., 20.);
11156        let r = _mm256_mask_unpacklo_pd(a, 0, a, b);
11157        assert_eq_m256d(r, a);
11158        let r = _mm256_mask_unpacklo_pd(a, 0b00001111, a, b);
11159        let e = _mm256_set_pd(18., 2., 20., 4.);
11160        assert_eq_m256d(r, e);
11161    }
11162
11163    #[simd_test(enable = "avx512f,avx512vl")]
11164    unsafe fn test_mm256_maskz_unpacklo_pd() {
11165        let a = _mm256_set_pd(1., 2., 3., 4.);
11166        let b = _mm256_set_pd(17., 18., 19., 20.);
11167        let r = _mm256_maskz_unpacklo_pd(0, a, b);
11168        assert_eq_m256d(r, _mm256_setzero_pd());
11169        let r = _mm256_maskz_unpacklo_pd(0b00001111, a, b);
11170        let e = _mm256_set_pd(18., 2., 20., 4.);
11171        assert_eq_m256d(r, e);
11172    }
11173
11174    #[simd_test(enable = "avx512f,avx512vl")]
11175    unsafe fn test_mm_mask_unpacklo_pd() {
11176        let a = _mm_set_pd(1., 2.);
11177        let b = _mm_set_pd(17., 18.);
11178        let r = _mm_mask_unpacklo_pd(a, 0, a, b);
11179        assert_eq_m128d(r, a);
11180        let r = _mm_mask_unpacklo_pd(a, 0b00000011, a, b);
11181        let e = _mm_set_pd(18., 2.);
11182        assert_eq_m128d(r, e);
11183    }
11184
11185    #[simd_test(enable = "avx512f,avx512vl")]
11186    unsafe fn test_mm_maskz_unpacklo_pd() {
11187        let a = _mm_set_pd(1., 2.);
11188        let b = _mm_set_pd(17., 18.);
11189        let r = _mm_maskz_unpacklo_pd(0, a, b);
11190        assert_eq_m128d(r, _mm_setzero_pd());
11191        let r = _mm_maskz_unpacklo_pd(0b00000011, a, b);
11192        let e = _mm_set_pd(18., 2.);
11193        assert_eq_m128d(r, e);
11194    }
11195
11196    #[simd_test(enable = "avx512f")]
11197    unsafe fn test_mm512_alignr_epi64() {
11198        let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
11199        let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
11200        let r = _mm512_alignr_epi64::<0>(a, b);
11201        assert_eq_m512i(r, b);
11202        let r = _mm512_alignr_epi64::<8>(a, b);
11203        assert_eq_m512i(r, b);
11204        let r = _mm512_alignr_epi64::<1>(a, b);
11205        let e = _mm512_set_epi64(1, 16, 15, 14, 13, 12, 11, 10);
11206        assert_eq_m512i(r, e);
11207    }
11208
11209    #[simd_test(enable = "avx512f")]
11210    unsafe fn test_mm512_mask_alignr_epi64() {
11211        let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
11212        let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
11213        let r = _mm512_mask_alignr_epi64::<1>(a, 0, a, b);
11214        assert_eq_m512i(r, a);
11215        let r = _mm512_mask_alignr_epi64::<1>(a, 0b11111111, a, b);
11216        let e = _mm512_set_epi64(1, 16, 15, 14, 13, 12, 11, 10);
11217        assert_eq_m512i(r, e);
11218    }
11219
11220    #[simd_test(enable = "avx512f")]
11221    unsafe fn test_mm512_maskz_alignr_epi64() {
11222        let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
11223        let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
11224        let r = _mm512_maskz_alignr_epi64::<1>(0, a, b);
11225        assert_eq_m512i(r, _mm512_setzero_si512());
11226        let r = _mm512_maskz_alignr_epi64::<1>(0b00001111, a, b);
11227        let e = _mm512_set_epi64(0, 0, 0, 0, 13, 12, 11, 10);
11228        assert_eq_m512i(r, e);
11229    }
11230
11231    #[simd_test(enable = "avx512f,avx512vl")]
11232    unsafe fn test_mm256_alignr_epi64() {
11233        let a = _mm256_set_epi64x(4, 3, 2, 1);
11234        let b = _mm256_set_epi64x(8, 7, 6, 5);
11235        let r = _mm256_alignr_epi64::<0>(a, b);
11236        let e = _mm256_set_epi64x(8, 7, 6, 5);
11237        assert_eq_m256i(r, e);
11238        let r = _mm256_alignr_epi64::<1>(a, b);
11239        let e = _mm256_set_epi64x(1, 8, 7, 6);
11240        assert_eq_m256i(r, e);
11241        let r = _mm256_alignr_epi64::<6>(a, b);
11242        let e = _mm256_set_epi64x(2, 1, 8, 7);
11243        assert_eq_m256i(r, e);
11244    }
11245
11246    #[simd_test(enable = "avx512f,avx512vl")]
11247    unsafe fn test_mm256_mask_alignr_epi64() {
11248        let a = _mm256_set_epi64x(4, 3, 2, 1);
11249        let b = _mm256_set_epi64x(8, 7, 6, 5);
11250        let r = _mm256_mask_alignr_epi64::<1>(a, 0, a, b);
11251        assert_eq_m256i(r, a);
11252        let r = _mm256_mask_alignr_epi64::<0>(a, 0b00001111, a, b);
11253        let e = _mm256_set_epi64x(8, 7, 6, 5);
11254        assert_eq_m256i(r, e);
11255    }
11256
11257    #[simd_test(enable = "avx512f,avx512vl")]
11258    unsafe fn test_mm256_maskz_alignr_epi64() {
11259        let a = _mm256_set_epi64x(4, 3, 2, 1);
11260        let b = _mm256_set_epi64x(8, 7, 6, 5);
11261        let r = _mm256_maskz_alignr_epi64::<1>(0, a, b);
11262        assert_eq_m256i(r, _mm256_setzero_si256());
11263        let r = _mm256_maskz_alignr_epi64::<0>(0b00001111, a, b);
11264        let e = _mm256_set_epi64x(8, 7, 6, 5);
11265        assert_eq_m256i(r, e);
11266    }
11267
11268    #[simd_test(enable = "avx512f,avx512vl")]
11269    unsafe fn test_mm_alignr_epi64() {
11270        let a = _mm_set_epi64x(2, 1);
11271        let b = _mm_set_epi64x(4, 3);
11272        let r = _mm_alignr_epi64::<0>(a, b);
11273        let e = _mm_set_epi64x(4, 3);
11274        assert_eq_m128i(r, e);
11275    }
11276
11277    #[simd_test(enable = "avx512f,avx512vl")]
11278    unsafe fn test_mm_mask_alignr_epi64() {
11279        let a = _mm_set_epi64x(2, 1);
11280        let b = _mm_set_epi64x(4, 3);
11281        let r = _mm_mask_alignr_epi64::<1>(a, 0, a, b);
11282        assert_eq_m128i(r, a);
11283        let r = _mm_mask_alignr_epi64::<0>(a, 0b00000011, a, b);
11284        let e = _mm_set_epi64x(4, 3);
11285        assert_eq_m128i(r, e);
11286    }
11287
11288    #[simd_test(enable = "avx512f,avx512vl")]
11289    unsafe fn test_mm_maskz_alignr_epi64() {
11290        let a = _mm_set_epi64x(2, 1);
11291        let b = _mm_set_epi64x(4, 3);
11292        let r = _mm_maskz_alignr_epi64::<1>(0, a, b);
11293        assert_eq_m128i(r, _mm_setzero_si128());
11294        let r = _mm_maskz_alignr_epi64::<0>(0b00000011, a, b);
11295        let e = _mm_set_epi64x(4, 3);
11296        assert_eq_m128i(r, e);
11297    }
11298
11299    #[simd_test(enable = "avx512f")]
11300    unsafe fn test_mm512_and_epi64() {
11301        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11302        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11303        let r = _mm512_and_epi64(a, b);
11304        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11305        assert_eq_m512i(r, e);
11306    }
11307
11308    #[simd_test(enable = "avx512f")]
11309    unsafe fn test_mm512_mask_and_epi64() {
11310        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11311        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11312        let r = _mm512_mask_and_epi64(a, 0, a, b);
11313        assert_eq_m512i(r, a);
11314        let r = _mm512_mask_and_epi64(a, 0b01111111, a, b);
11315        let e = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11316        assert_eq_m512i(r, e);
11317    }
11318
11319    #[simd_test(enable = "avx512f")]
11320    unsafe fn test_mm512_maskz_and_epi64() {
11321        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11322        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11323        let r = _mm512_maskz_and_epi64(0, a, b);
11324        assert_eq_m512i(r, _mm512_setzero_si512());
11325        let r = _mm512_maskz_and_epi64(0b00001111, a, b);
11326        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11327        assert_eq_m512i(r, e);
11328    }
11329
11330    #[simd_test(enable = "avx512f,avx512vl")]
11331    unsafe fn test_mm256_mask_and_epi64() {
11332        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11333        let b = _mm256_set1_epi64x(1 << 0);
11334        let r = _mm256_mask_and_epi64(a, 0, a, b);
11335        assert_eq_m256i(r, a);
11336        let r = _mm256_mask_and_epi64(a, 0b00001111, a, b);
11337        let e = _mm256_set1_epi64x(1 << 0);
11338        assert_eq_m256i(r, e);
11339    }
11340
11341    #[simd_test(enable = "avx512f,avx512vl")]
11342    unsafe fn test_mm256_maskz_and_epi64() {
11343        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11344        let b = _mm256_set1_epi64x(1 << 0);
11345        let r = _mm256_maskz_and_epi64(0, a, b);
11346        assert_eq_m256i(r, _mm256_setzero_si256());
11347        let r = _mm256_maskz_and_epi64(0b00001111, a, b);
11348        let e = _mm256_set1_epi64x(1 << 0);
11349        assert_eq_m256i(r, e);
11350    }
11351
11352    #[simd_test(enable = "avx512f,avx512vl")]
11353    unsafe fn test_mm_mask_and_epi64() {
11354        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11355        let b = _mm_set1_epi64x(1 << 0);
11356        let r = _mm_mask_and_epi64(a, 0, a, b);
11357        assert_eq_m128i(r, a);
11358        let r = _mm_mask_and_epi64(a, 0b00000011, a, b);
11359        let e = _mm_set1_epi64x(1 << 0);
11360        assert_eq_m128i(r, e);
11361    }
11362
11363    #[simd_test(enable = "avx512f,avx512vl")]
11364    unsafe fn test_mm_maskz_and_epi64() {
11365        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11366        let b = _mm_set1_epi64x(1 << 0);
11367        let r = _mm_maskz_and_epi64(0, a, b);
11368        assert_eq_m128i(r, _mm_setzero_si128());
11369        let r = _mm_maskz_and_epi64(0b00000011, a, b);
11370        let e = _mm_set1_epi64x(1 << 0);
11371        assert_eq_m128i(r, e);
11372    }
11373
11374    #[simd_test(enable = "avx512f")]
11375    unsafe fn test_mm512_and_si512() {
11376        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11377        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11378        let r = _mm512_and_epi64(a, b);
11379        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11380        assert_eq_m512i(r, e);
11381    }
11382
11383    #[simd_test(enable = "avx512f")]
11384    unsafe fn test_mm512_or_epi64() {
11385        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11386        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11387        let r = _mm512_or_epi64(a, b);
11388        #[rustfmt::skip]
11389        let e = _mm512_set_epi64(
11390            1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
11391            0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
11392        );
11393        assert_eq_m512i(r, e);
11394    }
11395
11396    #[simd_test(enable = "avx512f")]
11397    unsafe fn test_mm512_mask_or_epi64() {
11398        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11399        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11400        let r = _mm512_mask_or_epi64(a, 0, a, b);
11401        assert_eq_m512i(r, a);
11402        let r = _mm512_mask_or_epi64(a, 0b11111111, a, b);
11403        #[rustfmt::skip]
11404        let e = _mm512_set_epi64(
11405            1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
11406            0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
11407        );
11408        assert_eq_m512i(r, e);
11409    }
11410
11411    #[simd_test(enable = "avx512f")]
11412    unsafe fn test_mm512_maskz_or_epi64() {
11413        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11414        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11415        let r = _mm512_maskz_or_epi64(0, a, b);
11416        assert_eq_m512i(r, _mm512_setzero_si512());
11417        let r = _mm512_maskz_or_epi64(0b00001111, a, b);
11418        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11419        assert_eq_m512i(r, e);
11420    }
11421
11422    #[simd_test(enable = "avx512f,avx512vl")]
11423    unsafe fn test_mm256_or_epi64() {
11424        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11425        let b = _mm256_set1_epi64x(1 << 13);
11426        let r = _mm256_or_epi64(a, b);
11427        let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11428        assert_eq_m256i(r, e);
11429    }
11430
11431    #[simd_test(enable = "avx512f,avx512vl")]
11432    unsafe fn test_mm256_mask_or_epi64() {
11433        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11434        let b = _mm256_set1_epi64x(1 << 13);
11435        let r = _mm256_mask_or_epi64(a, 0, a, b);
11436        assert_eq_m256i(r, a);
11437        let r = _mm256_mask_or_epi64(a, 0b00001111, a, b);
11438        let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11439        assert_eq_m256i(r, e);
11440    }
11441
11442    #[simd_test(enable = "avx512f,avx512vl")]
11443    unsafe fn test_mm256_maskz_or_epi64() {
11444        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11445        let b = _mm256_set1_epi64x(1 << 13);
11446        let r = _mm256_maskz_or_epi64(0, a, b);
11447        assert_eq_m256i(r, _mm256_setzero_si256());
11448        let r = _mm256_maskz_or_epi64(0b00001111, a, b);
11449        let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11450        assert_eq_m256i(r, e);
11451    }
11452
11453    #[simd_test(enable = "avx512f,avx512vl")]
11454    unsafe fn test_mm_or_epi64() {
11455        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11456        let b = _mm_set1_epi64x(1 << 13);
11457        let r = _mm_or_epi64(a, b);
11458        let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11459        assert_eq_m128i(r, e);
11460    }
11461
11462    #[simd_test(enable = "avx512f,avx512vl")]
11463    unsafe fn test_mm_mask_or_epi64() {
11464        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11465        let b = _mm_set1_epi64x(1 << 13);
11466        let r = _mm_mask_or_epi64(a, 0, a, b);
11467        assert_eq_m128i(r, a);
11468        let r = _mm_mask_or_epi64(a, 0b00000011, a, b);
11469        let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11470        assert_eq_m128i(r, e);
11471    }
11472
11473    #[simd_test(enable = "avx512f,avx512vl")]
11474    unsafe fn test_mm_maskz_or_epi64() {
11475        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11476        let b = _mm_set1_epi64x(1 << 13);
11477        let r = _mm_maskz_or_epi64(0, a, b);
11478        assert_eq_m128i(r, _mm_setzero_si128());
11479        let r = _mm_maskz_or_epi64(0b00000011, a, b);
11480        let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11481        assert_eq_m128i(r, e);
11482    }
11483
11484    #[simd_test(enable = "avx512f")]
11485    unsafe fn test_mm512_or_si512() {
11486        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11487        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11488        let r = _mm512_or_epi64(a, b);
11489        #[rustfmt::skip]
11490        let e = _mm512_set_epi64(
11491            1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
11492            0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
11493        );
11494        assert_eq_m512i(r, e);
11495    }
11496
11497    #[simd_test(enable = "avx512f")]
11498    unsafe fn test_mm512_xor_epi64() {
11499        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11500        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11501        let r = _mm512_xor_epi64(a, b);
11502        let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
11503        assert_eq_m512i(r, e);
11504    }
11505
11506    #[simd_test(enable = "avx512f")]
11507    unsafe fn test_mm512_mask_xor_epi64() {
11508        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11509        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11510        let r = _mm512_mask_xor_epi64(a, 0, a, b);
11511        assert_eq_m512i(r, a);
11512        let r = _mm512_mask_xor_epi64(a, 0b11111111, a, b);
11513        let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
11514        assert_eq_m512i(r, e);
11515    }
11516
11517    #[simd_test(enable = "avx512f")]
11518    unsafe fn test_mm512_maskz_xor_epi64() {
11519        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11520        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11521        let r = _mm512_maskz_xor_epi64(0, a, b);
11522        assert_eq_m512i(r, _mm512_setzero_si512());
11523        let r = _mm512_maskz_xor_epi64(0b00001111, a, b);
11524        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 0);
11525        assert_eq_m512i(r, e);
11526    }
11527
11528    #[simd_test(enable = "avx512f,avx512vl")]
11529    unsafe fn test_mm256_xor_epi64() {
11530        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11531        let b = _mm256_set1_epi64x(1 << 13);
11532        let r = _mm256_xor_epi64(a, b);
11533        let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11534        assert_eq_m256i(r, e);
11535    }
11536
11537    #[simd_test(enable = "avx512f,avx512vl")]
11538    unsafe fn test_mm256_mask_xor_epi64() {
11539        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11540        let b = _mm256_set1_epi64x(1 << 13);
11541        let r = _mm256_mask_xor_epi64(a, 0, a, b);
11542        assert_eq_m256i(r, a);
11543        let r = _mm256_mask_xor_epi64(a, 0b00001111, a, b);
11544        let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11545        assert_eq_m256i(r, e);
11546    }
11547
11548    #[simd_test(enable = "avx512f,avx512vl")]
11549    unsafe fn test_mm256_maskz_xor_epi64() {
11550        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11551        let b = _mm256_set1_epi64x(1 << 13);
11552        let r = _mm256_maskz_xor_epi64(0, a, b);
11553        assert_eq_m256i(r, _mm256_setzero_si256());
11554        let r = _mm256_maskz_xor_epi64(0b00001111, a, b);
11555        let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11556        assert_eq_m256i(r, e);
11557    }
11558
11559    #[simd_test(enable = "avx512f,avx512vl")]
11560    unsafe fn test_mm_xor_epi64() {
11561        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11562        let b = _mm_set1_epi64x(1 << 13);
11563        let r = _mm_xor_epi64(a, b);
11564        let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11565        assert_eq_m128i(r, e);
11566    }
11567
11568    #[simd_test(enable = "avx512f,avx512vl")]
11569    unsafe fn test_mm_mask_xor_epi64() {
11570        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11571        let b = _mm_set1_epi64x(1 << 13);
11572        let r = _mm_mask_xor_epi64(a, 0, a, b);
11573        assert_eq_m128i(r, a);
11574        let r = _mm_mask_xor_epi64(a, 0b00000011, a, b);
11575        let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11576        assert_eq_m128i(r, e);
11577    }
11578
11579    #[simd_test(enable = "avx512f,avx512vl")]
11580    unsafe fn test_mm_maskz_xor_epi64() {
11581        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11582        let b = _mm_set1_epi64x(1 << 13);
11583        let r = _mm_maskz_xor_epi64(0, a, b);
11584        assert_eq_m128i(r, _mm_setzero_si128());
11585        let r = _mm_maskz_xor_epi64(0b00000011, a, b);
11586        let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11587        assert_eq_m128i(r, e);
11588    }
11589
11590    #[simd_test(enable = "avx512f")]
11591    unsafe fn test_mm512_xor_si512() {
11592        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11593        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11594        let r = _mm512_xor_epi64(a, b);
11595        let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
11596        assert_eq_m512i(r, e);
11597    }
11598
11599    #[simd_test(enable = "avx512f")]
11600    unsafe fn test_mm512_andnot_epi64() {
11601        let a = _mm512_set1_epi64(0);
11602        let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11603        let r = _mm512_andnot_epi64(a, b);
11604        let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
11605        assert_eq_m512i(r, e);
11606    }
11607
11608    #[simd_test(enable = "avx512f")]
11609    unsafe fn test_mm512_mask_andnot_epi64() {
11610        let a = _mm512_set1_epi64(1 << 1 | 1 << 2);
11611        let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11612        let r = _mm512_mask_andnot_epi64(a, 0, a, b);
11613        assert_eq_m512i(r, a);
11614        let r = _mm512_mask_andnot_epi64(a, 0b11111111, a, b);
11615        let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
11616        assert_eq_m512i(r, e);
11617    }
11618
11619    #[simd_test(enable = "avx512f")]
11620    unsafe fn test_mm512_maskz_andnot_epi64() {
11621        let a = _mm512_set1_epi64(1 << 1 | 1 << 2);
11622        let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11623        let r = _mm512_maskz_andnot_epi64(0, a, b);
11624        assert_eq_m512i(r, _mm512_setzero_si512());
11625        let r = _mm512_maskz_andnot_epi64(0b00001111, a, b);
11626        #[rustfmt::skip]
11627        let e = _mm512_set_epi64(
11628            0, 0, 0, 0,
11629            1 << 3 | 1 << 4, 1 << 3 | 1 << 4, 1 << 3 | 1 << 4, 1 << 3 | 1 << 4,
11630        );
11631        assert_eq_m512i(r, e);
11632    }
11633
11634    #[simd_test(enable = "avx512f,avx512vl")]
11635    unsafe fn test_mm256_mask_andnot_epi64() {
11636        let a = _mm256_set1_epi64x(1 << 1 | 1 << 2);
11637        let b = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11638        let r = _mm256_mask_andnot_epi64(a, 0, a, b);
11639        assert_eq_m256i(r, a);
11640        let r = _mm256_mask_andnot_epi64(a, 0b00001111, a, b);
11641        let e = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11642        assert_eq_m256i(r, e);
11643    }
11644
11645    #[simd_test(enable = "avx512f,avx512vl")]
11646    unsafe fn test_mm256_maskz_andnot_epi64() {
11647        let a = _mm256_set1_epi64x(1 << 1 | 1 << 2);
11648        let b = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11649        let r = _mm256_maskz_andnot_epi64(0, a, b);
11650        assert_eq_m256i(r, _mm256_setzero_si256());
11651        let r = _mm256_maskz_andnot_epi64(0b00001111, a, b);
11652        let e = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11653        assert_eq_m256i(r, e);
11654    }
11655
11656    #[simd_test(enable = "avx512f,avx512vl")]
11657    unsafe fn test_mm_mask_andnot_epi64() {
11658        let a = _mm_set1_epi64x(1 << 1 | 1 << 2);
11659        let b = _mm_set1_epi64x(1 << 3 | 1 << 4);
11660        let r = _mm_mask_andnot_epi64(a, 0, a, b);
11661        assert_eq_m128i(r, a);
11662        let r = _mm_mask_andnot_epi64(a, 0b00000011, a, b);
11663        let e = _mm_set1_epi64x(1 << 3 | 1 << 4);
11664        assert_eq_m128i(r, e);
11665    }
11666
11667    #[simd_test(enable = "avx512f,avx512vl")]
11668    unsafe fn test_mm_maskz_andnot_epi64() {
11669        let a = _mm_set1_epi64x(1 << 1 | 1 << 2);
11670        let b = _mm_set1_epi64x(1 << 3 | 1 << 4);
11671        let r = _mm_maskz_andnot_epi64(0, a, b);
11672        assert_eq_m128i(r, _mm_setzero_si128());
11673        let r = _mm_maskz_andnot_epi64(0b00000011, a, b);
11674        let e = _mm_set1_epi64x(1 << 3 | 1 << 4);
11675        assert_eq_m128i(r, e);
11676    }
11677
11678    #[simd_test(enable = "avx512f")]
11679    unsafe fn test_mm512_andnot_si512() {
11680        let a = _mm512_set1_epi64(0);
11681        let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11682        let r = _mm512_andnot_si512(a, b);
11683        let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
11684        assert_eq_m512i(r, e);
11685    }
11686
11687    #[simd_test(enable = "avx512f")]
11688    unsafe fn test_mm512_reduce_add_epi64() {
11689        let a = _mm512_set1_epi64(1);
11690        let e: i64 = _mm512_reduce_add_epi64(a);
11691        assert_eq!(8, e);
11692    }
11693
11694    #[simd_test(enable = "avx512f")]
11695    unsafe fn test_mm512_mask_reduce_add_epi64() {
11696        let a = _mm512_set1_epi64(1);
11697        let e: i64 = _mm512_mask_reduce_add_epi64(0b11110000, a);
11698        assert_eq!(4, e);
11699    }
11700
11701    #[simd_test(enable = "avx512f")]
11702    unsafe fn test_mm512_reduce_add_pd() {
11703        let a = _mm512_set1_pd(1.);
11704        let e: f64 = _mm512_reduce_add_pd(a);
11705        assert_eq!(8., e);
11706    }
11707
11708    #[simd_test(enable = "avx512f")]
11709    unsafe fn test_mm512_mask_reduce_add_pd() {
11710        let a = _mm512_set1_pd(1.);
11711        let e: f64 = _mm512_mask_reduce_add_pd(0b11110000, a);
11712        assert_eq!(4., e);
11713    }
11714
11715    #[simd_test(enable = "avx512f")]
11716    unsafe fn test_mm512_reduce_mul_epi64() {
11717        let a = _mm512_set1_epi64(2);
11718        let e: i64 = _mm512_reduce_mul_epi64(a);
11719        assert_eq!(256, e);
11720    }
11721
11722    #[simd_test(enable = "avx512f")]
11723    unsafe fn test_mm512_mask_reduce_mul_epi64() {
11724        let a = _mm512_set1_epi64(2);
11725        let e: i64 = _mm512_mask_reduce_mul_epi64(0b11110000, a);
11726        assert_eq!(16, e);
11727    }
11728
11729    #[simd_test(enable = "avx512f")]
11730    unsafe fn test_mm512_reduce_mul_pd() {
11731        let a = _mm512_set1_pd(2.);
11732        let e: f64 = _mm512_reduce_mul_pd(a);
11733        assert_eq!(256., e);
11734    }
11735
11736    #[simd_test(enable = "avx512f")]
11737    unsafe fn test_mm512_mask_reduce_mul_pd() {
11738        let a = _mm512_set1_pd(2.);
11739        let e: f64 = _mm512_mask_reduce_mul_pd(0b11110000, a);
11740        assert_eq!(16., e);
11741    }
11742
11743    #[simd_test(enable = "avx512f")]
11744    unsafe fn test_mm512_reduce_max_epi64() {
11745        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11746        let e: i64 = _mm512_reduce_max_epi64(a);
11747        assert_eq!(7, e);
11748    }
11749
11750    #[simd_test(enable = "avx512f")]
11751    unsafe fn test_mm512_mask_reduce_max_epi64() {
11752        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11753        let e: i64 = _mm512_mask_reduce_max_epi64(0b11110000, a);
11754        assert_eq!(3, e);
11755    }
11756
11757    #[simd_test(enable = "avx512f")]
11758    unsafe fn test_mm512_reduce_max_epu64() {
11759        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11760        let e: u64 = _mm512_reduce_max_epu64(a);
11761        assert_eq!(7, e);
11762    }
11763
11764    #[simd_test(enable = "avx512f")]
11765    unsafe fn test_mm512_mask_reduce_max_epu64() {
11766        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11767        let e: u64 = _mm512_mask_reduce_max_epu64(0b11110000, a);
11768        assert_eq!(3, e);
11769    }
11770
11771    #[simd_test(enable = "avx512f")]
11772    unsafe fn test_mm512_reduce_max_pd() {
11773        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11774        let e: f64 = _mm512_reduce_max_pd(a);
11775        assert_eq!(7., e);
11776    }
11777
11778    #[simd_test(enable = "avx512f")]
11779    unsafe fn test_mm512_mask_reduce_max_pd() {
11780        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11781        let e: f64 = _mm512_mask_reduce_max_pd(0b11110000, a);
11782        assert_eq!(3., e);
11783    }
11784
11785    #[simd_test(enable = "avx512f")]
11786    unsafe fn test_mm512_reduce_min_epi64() {
11787        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11788        let e: i64 = _mm512_reduce_min_epi64(a);
11789        assert_eq!(0, e);
11790    }
11791
11792    #[simd_test(enable = "avx512f")]
11793    unsafe fn test_mm512_mask_reduce_min_epi64() {
11794        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11795        let e: i64 = _mm512_mask_reduce_min_epi64(0b11110000, a);
11796        assert_eq!(0, e);
11797    }
11798
11799    #[simd_test(enable = "avx512f")]
11800    unsafe fn test_mm512_reduce_min_epu64() {
11801        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11802        let e: u64 = _mm512_reduce_min_epu64(a);
11803        assert_eq!(0, e);
11804    }
11805
11806    #[simd_test(enable = "avx512f")]
11807    unsafe fn test_mm512_mask_reduce_min_epu64() {
11808        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11809        let e: u64 = _mm512_mask_reduce_min_epu64(0b11110000, a);
11810        assert_eq!(0, e);
11811    }
11812
11813    #[simd_test(enable = "avx512f")]
11814    unsafe fn test_mm512_reduce_min_pd() {
11815        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11816        let e: f64 = _mm512_reduce_min_pd(a);
11817        assert_eq!(0., e);
11818    }
11819
11820    #[simd_test(enable = "avx512f")]
11821    unsafe fn test_mm512_mask_reduce_min_pd() {
11822        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11823        let e: f64 = _mm512_mask_reduce_min_pd(0b11110000, a);
11824        assert_eq!(0., e);
11825    }
11826
11827    #[simd_test(enable = "avx512f")]
11828    unsafe fn test_mm512_reduce_and_epi64() {
11829        let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11830        let e: i64 = _mm512_reduce_and_epi64(a);
11831        assert_eq!(0, e);
11832    }
11833
11834    #[simd_test(enable = "avx512f")]
11835    unsafe fn test_mm512_mask_reduce_and_epi64() {
11836        let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11837        let e: i64 = _mm512_mask_reduce_and_epi64(0b11110000, a);
11838        assert_eq!(1, e);
11839    }
11840
11841    #[simd_test(enable = "avx512f")]
11842    unsafe fn test_mm512_reduce_or_epi64() {
11843        let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11844        let e: i64 = _mm512_reduce_or_epi64(a);
11845        assert_eq!(3, e);
11846    }
11847
11848    #[simd_test(enable = "avx512f")]
11849    unsafe fn test_mm512_mask_reduce_or_epi64() {
11850        let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11851        let e: i64 = _mm512_mask_reduce_or_epi64(0b11110000, a);
11852        assert_eq!(1, e);
11853    }
11854
11855    #[simd_test(enable = "avx512f")]
11856    unsafe fn test_mm512_extractf64x4_pd() {
11857        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11858        let r = _mm512_extractf64x4_pd::<1>(a);
11859        let e = _mm256_setr_pd(5., 6., 7., 8.);
11860        assert_eq_m256d(r, e);
11861    }
11862
11863    #[simd_test(enable = "avx512f")]
11864    unsafe fn test_mm512_mask_extractf64x4_pd() {
11865        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11866        let src = _mm256_set1_pd(100.);
11867        let r = _mm512_mask_extractf64x4_pd::<1>(src, 0, a);
11868        assert_eq_m256d(r, src);
11869        let r = _mm512_mask_extractf64x4_pd::<1>(src, 0b11111111, a);
11870        let e = _mm256_setr_pd(5., 6., 7., 8.);
11871        assert_eq_m256d(r, e);
11872    }
11873
11874    #[simd_test(enable = "avx512f")]
11875    unsafe fn test_mm512_maskz_extractf64x4_pd() {
11876        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11877        let r = _mm512_maskz_extractf64x4_pd::<1>(0, a);
11878        assert_eq_m256d(r, _mm256_setzero_pd());
11879        let r = _mm512_maskz_extractf64x4_pd::<1>(0b00000001, a);
11880        let e = _mm256_setr_pd(5., 0., 0., 0.);
11881        assert_eq_m256d(r, e);
11882    }
11883
11884    #[simd_test(enable = "avx512f")]
11885    unsafe fn test_mm512_extracti64x4_epi64() {
11886        let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11887        let r = _mm512_extracti64x4_epi64::<0x1>(a);
11888        let e = _mm256_setr_epi64x(5, 6, 7, 8);
11889        assert_eq_m256i(r, e);
11890    }
11891
11892    #[simd_test(enable = "avx512f")]
11893    unsafe fn test_mm512_mask_extracti64x4_epi64() {
11894        let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11895        let src = _mm256_set1_epi64x(100);
11896        let r = _mm512_mask_extracti64x4_epi64::<0x1>(src, 0, a);
11897        assert_eq_m256i(r, src);
11898        let r = _mm512_mask_extracti64x4_epi64::<0x1>(src, 0b11111111, a);
11899        let e = _mm256_setr_epi64x(5, 6, 7, 8);
11900        assert_eq_m256i(r, e);
11901    }
11902
11903    #[simd_test(enable = "avx512f")]
11904    unsafe fn test_mm512_maskz_extracti64x4_epi64() {
11905        let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11906        let r = _mm512_maskz_extracti64x4_epi64::<0x1>(0, a);
11907        assert_eq_m256i(r, _mm256_setzero_si256());
11908        let r = _mm512_maskz_extracti64x4_epi64::<0x1>(0b00000001, a);
11909        let e = _mm256_setr_epi64x(5, 0, 0, 0);
11910        assert_eq_m256i(r, e);
11911    }
11912
11913    #[simd_test(enable = "avx512f")]
11914    unsafe fn test_mm512_mask_compress_epi64() {
11915        let src = _mm512_set1_epi64(200);
11916        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11917        let r = _mm512_mask_compress_epi64(src, 0, a);
11918        assert_eq_m512i(r, src);
11919        let r = _mm512_mask_compress_epi64(src, 0b01010101, a);
11920        let e = _mm512_set_epi64(200, 200, 200, 200, 1, 3, 5, 7);
11921        assert_eq_m512i(r, e);
11922    }
11923
11924    #[simd_test(enable = "avx512f")]
11925    unsafe fn test_mm512_maskz_compress_epi64() {
11926        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11927        let r = _mm512_maskz_compress_epi64(0, a);
11928        assert_eq_m512i(r, _mm512_setzero_si512());
11929        let r = _mm512_maskz_compress_epi64(0b01010101, a);
11930        let e = _mm512_set_epi64(0, 0, 0, 0, 1, 3, 5, 7);
11931        assert_eq_m512i(r, e);
11932    }
11933
11934    #[simd_test(enable = "avx512f,avx512vl")]
11935    unsafe fn test_mm256_mask_compress_epi64() {
11936        let src = _mm256_set1_epi64x(200);
11937        let a = _mm256_set_epi64x(0, 1, 2, 3);
11938        let r = _mm256_mask_compress_epi64(src, 0, a);
11939        assert_eq_m256i(r, src);
11940        let r = _mm256_mask_compress_epi64(src, 0b00000101, a);
11941        let e = _mm256_set_epi64x(200, 200, 1, 3);
11942        assert_eq_m256i(r, e);
11943    }
11944
11945    #[simd_test(enable = "avx512f,avx512vl")]
11946    unsafe fn test_mm256_maskz_compress_epi64() {
11947        let a = _mm256_set_epi64x(0, 1, 2, 3);
11948        let r = _mm256_maskz_compress_epi64(0, a);
11949        assert_eq_m256i(r, _mm256_setzero_si256());
11950        let r = _mm256_maskz_compress_epi64(0b00000101, a);
11951        let e = _mm256_set_epi64x(0, 0, 1, 3);
11952        assert_eq_m256i(r, e);
11953    }
11954
11955    #[simd_test(enable = "avx512f,avx512vl")]
11956    unsafe fn test_mm_mask_compress_epi64() {
11957        let src = _mm_set1_epi64x(200);
11958        let a = _mm_set_epi64x(0, 1);
11959        let r = _mm_mask_compress_epi64(src, 0, a);
11960        assert_eq_m128i(r, src);
11961        let r = _mm_mask_compress_epi64(src, 0b00000001, a);
11962        let e = _mm_set_epi64x(200, 1);
11963        assert_eq_m128i(r, e);
11964    }
11965
11966    #[simd_test(enable = "avx512f,avx512vl")]
11967    unsafe fn test_mm_maskz_compress_epi64() {
11968        let a = _mm_set_epi64x(0, 1);
11969        let r = _mm_maskz_compress_epi64(0, a);
11970        assert_eq_m128i(r, _mm_setzero_si128());
11971        let r = _mm_maskz_compress_epi64(0b00000001, a);
11972        let e = _mm_set_epi64x(0, 1);
11973        assert_eq_m128i(r, e);
11974    }
11975
11976    #[simd_test(enable = "avx512f")]
11977    unsafe fn test_mm512_mask_compress_pd() {
11978        let src = _mm512_set1_pd(200.);
11979        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11980        let r = _mm512_mask_compress_pd(src, 0, a);
11981        assert_eq_m512d(r, src);
11982        let r = _mm512_mask_compress_pd(src, 0b01010101, a);
11983        let e = _mm512_set_pd(200., 200., 200., 200., 1., 3., 5., 7.);
11984        assert_eq_m512d(r, e);
11985    }
11986
11987    #[simd_test(enable = "avx512f")]
11988    unsafe fn test_mm512_maskz_compress_pd() {
11989        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11990        let r = _mm512_maskz_compress_pd(0, a);
11991        assert_eq_m512d(r, _mm512_setzero_pd());
11992        let r = _mm512_maskz_compress_pd(0b01010101, a);
11993        let e = _mm512_set_pd(0., 0., 0., 0., 1., 3., 5., 7.);
11994        assert_eq_m512d(r, e);
11995    }
11996
11997    #[simd_test(enable = "avx512f,avx512vl")]
11998    unsafe fn test_mm256_mask_compress_pd() {
11999        let src = _mm256_set1_pd(200.);
12000        let a = _mm256_set_pd(0., 1., 2., 3.);
12001        let r = _mm256_mask_compress_pd(src, 0, a);
12002        assert_eq_m256d(r, src);
12003        let r = _mm256_mask_compress_pd(src, 0b00000101, a);
12004        let e = _mm256_set_pd(200., 200., 1., 3.);
12005        assert_eq_m256d(r, e);
12006    }
12007
12008    #[simd_test(enable = "avx512f,avx512vl")]
12009    unsafe fn test_mm256_maskz_compress_pd() {
12010        let a = _mm256_set_pd(0., 1., 2., 3.);
12011        let r = _mm256_maskz_compress_pd(0, a);
12012        assert_eq_m256d(r, _mm256_setzero_pd());
12013        let r = _mm256_maskz_compress_pd(0b00000101, a);
12014        let e = _mm256_set_pd(0., 0., 1., 3.);
12015        assert_eq_m256d(r, e);
12016    }
12017
12018    #[simd_test(enable = "avx512f,avx512vl")]
12019    unsafe fn test_mm_mask_compress_pd() {
12020        let src = _mm_set1_pd(200.);
12021        let a = _mm_set_pd(0., 1.);
12022        let r = _mm_mask_compress_pd(src, 0, a);
12023        assert_eq_m128d(r, src);
12024        let r = _mm_mask_compress_pd(src, 0b00000001, a);
12025        let e = _mm_set_pd(200., 1.);
12026        assert_eq_m128d(r, e);
12027    }
12028
12029    #[simd_test(enable = "avx512f,avx512vl")]
12030    unsafe fn test_mm_maskz_compress_pd() {
12031        let a = _mm_set_pd(0., 1.);
12032        let r = _mm_maskz_compress_pd(0, a);
12033        assert_eq_m128d(r, _mm_setzero_pd());
12034        let r = _mm_maskz_compress_pd(0b00000001, a);
12035        let e = _mm_set_pd(0., 1.);
12036        assert_eq_m128d(r, e);
12037    }
12038
12039    #[simd_test(enable = "avx512f")]
12040    unsafe fn test_mm512_mask_expand_epi64() {
12041        let src = _mm512_set1_epi64(200);
12042        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
12043        let r = _mm512_mask_expand_epi64(src, 0, a);
12044        assert_eq_m512i(r, src);
12045        let r = _mm512_mask_expand_epi64(src, 0b01010101, a);
12046        let e = _mm512_set_epi64(200, 4, 200, 5, 200, 6, 200, 7);
12047        assert_eq_m512i(r, e);
12048    }
12049
12050    #[simd_test(enable = "avx512f")]
12051    unsafe fn test_mm512_maskz_expand_epi64() {
12052        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
12053        let r = _mm512_maskz_expand_epi64(0, a);
12054        assert_eq_m512i(r, _mm512_setzero_si512());
12055        let r = _mm512_maskz_expand_epi64(0b01010101, a);
12056        let e = _mm512_set_epi64(0, 4, 0, 5, 0, 6, 0, 7);
12057        assert_eq_m512i(r, e);
12058    }
12059
12060    #[simd_test(enable = "avx512f,avx512vl")]
12061    unsafe fn test_mm256_mask_expand_epi64() {
12062        let src = _mm256_set1_epi64x(200);
12063        let a = _mm256_set_epi64x(0, 1, 2, 3);
12064        let r = _mm256_mask_expand_epi64(src, 0, a);
12065        assert_eq_m256i(r, src);
12066        let r = _mm256_mask_expand_epi64(src, 0b00000101, a);
12067        let e = _mm256_set_epi64x(200, 2, 200, 3);
12068        assert_eq_m256i(r, e);
12069    }
12070
12071    #[simd_test(enable = "avx512f,avx512vl")]
12072    unsafe fn test_mm256_maskz_expand_epi64() {
12073        let a = _mm256_set_epi64x(0, 1, 2, 3);
12074        let r = _mm256_maskz_expand_epi64(0, a);
12075        assert_eq_m256i(r, _mm256_setzero_si256());
12076        let r = _mm256_maskz_expand_epi64(0b00000101, a);
12077        let e = _mm256_set_epi64x(0, 2, 0, 3);
12078        assert_eq_m256i(r, e);
12079    }
12080
12081    #[simd_test(enable = "avx512f,avx512vl")]
12082    unsafe fn test_mm_mask_expand_epi64() {
12083        let src = _mm_set1_epi64x(200);
12084        let a = _mm_set_epi64x(0, 1);
12085        let r = _mm_mask_expand_epi64(src, 0, a);
12086        assert_eq_m128i(r, src);
12087        let r = _mm_mask_expand_epi64(src, 0b00000001, a);
12088        let e = _mm_set_epi64x(200, 1);
12089        assert_eq_m128i(r, e);
12090    }
12091
12092    #[simd_test(enable = "avx512f,avx512vl")]
12093    unsafe fn test_mm_maskz_expand_epi64() {
12094        let a = _mm_set_epi64x(0, 1);
12095        let r = _mm_maskz_expand_epi64(0, a);
12096        assert_eq_m128i(r, _mm_setzero_si128());
12097        let r = _mm_maskz_expand_epi64(0b00000001, a);
12098        let e = _mm_set_epi64x(0, 1);
12099        assert_eq_m128i(r, e);
12100    }
12101
12102    #[simd_test(enable = "avx512f")]
12103    unsafe fn test_mm512_mask_expand_pd() {
12104        let src = _mm512_set1_pd(200.);
12105        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
12106        let r = _mm512_mask_expand_pd(src, 0, a);
12107        assert_eq_m512d(r, src);
12108        let r = _mm512_mask_expand_pd(src, 0b01010101, a);
12109        let e = _mm512_set_pd(200., 4., 200., 5., 200., 6., 200., 7.);
12110        assert_eq_m512d(r, e);
12111    }
12112
12113    #[simd_test(enable = "avx512f")]
12114    unsafe fn test_mm512_maskz_expand_pd() {
12115        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
12116        let r = _mm512_maskz_expand_pd(0, a);
12117        assert_eq_m512d(r, _mm512_setzero_pd());
12118        let r = _mm512_maskz_expand_pd(0b01010101, a);
12119        let e = _mm512_set_pd(0., 4., 0., 5., 0., 6., 0., 7.);
12120        assert_eq_m512d(r, e);
12121    }
12122
12123    #[simd_test(enable = "avx512f,avx512vl")]
12124    unsafe fn test_mm256_mask_expand_pd() {
12125        let src = _mm256_set1_pd(200.);
12126        let a = _mm256_set_pd(0., 1., 2., 3.);
12127        let r = _mm256_mask_expand_pd(src, 0, a);
12128        assert_eq_m256d(r, src);
12129        let r = _mm256_mask_expand_pd(src, 0b00000101, a);
12130        let e = _mm256_set_pd(200., 2., 200., 3.);
12131        assert_eq_m256d(r, e);
12132    }
12133
12134    #[simd_test(enable = "avx512f,avx512vl")]
12135    unsafe fn test_mm256_maskz_expand_pd() {
12136        let a = _mm256_set_pd(0., 1., 2., 3.);
12137        let r = _mm256_maskz_expand_pd(0, a);
12138        assert_eq_m256d(r, _mm256_setzero_pd());
12139        let r = _mm256_maskz_expand_pd(0b00000101, a);
12140        let e = _mm256_set_pd(0., 2., 0., 3.);
12141        assert_eq_m256d(r, e);
12142    }
12143
12144    #[simd_test(enable = "avx512f,avx512vl")]
12145    unsafe fn test_mm_mask_expand_pd() {
12146        let src = _mm_set1_pd(200.);
12147        let a = _mm_set_pd(0., 1.);
12148        let r = _mm_mask_expand_pd(src, 0, a);
12149        assert_eq_m128d(r, src);
12150        let r = _mm_mask_expand_pd(src, 0b00000001, a);
12151        let e = _mm_set_pd(200., 1.);
12152        assert_eq_m128d(r, e);
12153    }
12154
12155    #[simd_test(enable = "avx512f,avx512vl")]
12156    unsafe fn test_mm_maskz_expand_pd() {
12157        let a = _mm_set_pd(0., 1.);
12158        let r = _mm_maskz_expand_pd(0, a);
12159        assert_eq_m128d(r, _mm_setzero_pd());
12160        let r = _mm_maskz_expand_pd(0b00000001, a);
12161        let e = _mm_set_pd(0., 1.);
12162        assert_eq_m128d(r, e);
12163    }
12164
12165    #[simd_test(enable = "avx512f")]
12166    unsafe fn test_mm512_loadu_epi64() {
12167        let a = &[4, 3, 2, 5, -8, -9, -64, -50];
12168        let p = a.as_ptr();
12169        let r = _mm512_loadu_epi64(black_box(p));
12170        let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50);
12171        assert_eq_m512i(r, e);
12172    }
12173
12174    #[simd_test(enable = "avx512f,avx512vl")]
12175    unsafe fn test_mm256_loadu_epi64() {
12176        let a = &[4, 3, 2, 5];
12177        let p = a.as_ptr();
12178        let r = _mm256_loadu_epi64(black_box(p));
12179        let e = _mm256_setr_epi64x(4, 3, 2, 5);
12180        assert_eq_m256i(r, e);
12181    }
12182
12183    #[simd_test(enable = "avx512f,avx512vl")]
12184    unsafe fn test_mm_loadu_epi64() {
12185        let a = &[4, 3];
12186        let p = a.as_ptr();
12187        let r = _mm_loadu_epi64(black_box(p));
12188        let e = _mm_setr_epi64x(4, 3);
12189        assert_eq_m128i(r, e);
12190    }
12191
12192    #[simd_test(enable = "avx512f")]
12193    unsafe fn test_mm512_mask_cvtepi64_storeu_epi16() {
12194        let a = _mm512_set1_epi64(9);
12195        let mut r = _mm_undefined_si128();
12196        _mm512_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12197        let e = _mm_set1_epi16(9);
12198        assert_eq_m128i(r, e);
12199    }
12200
12201    #[simd_test(enable = "avx512f,avx512vl")]
12202    unsafe fn test_mm256_mask_cvtepi64_storeu_epi16() {
12203        let a = _mm256_set1_epi64x(9);
12204        let mut r = _mm_set1_epi16(0);
12205        _mm256_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12206        let e = _mm_set_epi16(0, 0, 0, 0, 9, 9, 9, 9);
12207        assert_eq_m128i(r, e);
12208    }
12209
12210    #[simd_test(enable = "avx512f,avx512vl")]
12211    unsafe fn test_mm_mask_cvtepi64_storeu_epi16() {
12212        let a = _mm_set1_epi64x(9);
12213        let mut r = _mm_set1_epi16(0);
12214        _mm_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12215        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 9, 9);
12216        assert_eq_m128i(r, e);
12217    }
12218
12219    #[simd_test(enable = "avx512f")]
12220    unsafe fn test_mm512_mask_cvtsepi64_storeu_epi16() {
12221        let a = _mm512_set1_epi64(i64::MAX);
12222        let mut r = _mm_undefined_si128();
12223        _mm512_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12224        let e = _mm_set1_epi16(i16::MAX);
12225        assert_eq_m128i(r, e);
12226    }
12227
12228    #[simd_test(enable = "avx512f,avx512vl")]
12229    unsafe fn test_mm256_mask_cvtsepi64_storeu_epi16() {
12230        let a = _mm256_set1_epi64x(i64::MAX);
12231        let mut r = _mm_set1_epi16(0);
12232        _mm256_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12233        let e = _mm_set_epi16(0, 0, 0, 0, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
12234        assert_eq_m128i(r, e);
12235    }
12236
12237    #[simd_test(enable = "avx512f,avx512vl")]
12238    unsafe fn test_mm_mask_cvtsepi64_storeu_epi16() {
12239        let a = _mm_set1_epi64x(i64::MAX);
12240        let mut r = _mm_set1_epi16(0);
12241        _mm_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12242        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MAX, i16::MAX);
12243        assert_eq_m128i(r, e);
12244    }
12245
12246    #[simd_test(enable = "avx512f")]
12247    unsafe fn test_mm512_mask_cvtusepi64_storeu_epi16() {
12248        let a = _mm512_set1_epi64(i64::MAX);
12249        let mut r = _mm_undefined_si128();
12250        _mm512_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12251        let e = _mm_set1_epi16(u16::MAX as i16);
12252        assert_eq_m128i(r, e);
12253    }
12254
12255    #[simd_test(enable = "avx512f,avx512vl")]
12256    unsafe fn test_mm256_mask_cvtusepi64_storeu_epi16() {
12257        let a = _mm256_set1_epi64x(i64::MAX);
12258        let mut r = _mm_set1_epi16(0);
12259        _mm256_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12260        let e = _mm_set_epi16(
12261            0,
12262            0,
12263            0,
12264            0,
12265            u16::MAX as i16,
12266            u16::MAX as i16,
12267            u16::MAX as i16,
12268            u16::MAX as i16,
12269        );
12270        assert_eq_m128i(r, e);
12271    }
12272
12273    #[simd_test(enable = "avx512f,avx512vl")]
12274    unsafe fn test_mm_mask_cvtusepi64_storeu_epi16() {
12275        let a = _mm_set1_epi64x(i64::MAX);
12276        let mut r = _mm_set1_epi16(0);
12277        _mm_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12278        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, u16::MAX as i16, u16::MAX as i16);
12279        assert_eq_m128i(r, e);
12280    }
12281
12282    #[simd_test(enable = "avx512f")]
12283    unsafe fn test_mm512_mask_cvtepi64_storeu_epi8() {
12284        let a = _mm512_set1_epi64(9);
12285        let mut r = _mm_set1_epi8(0);
12286        _mm512_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12287        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 9, 9, 9, 9);
12288        assert_eq_m128i(r, e);
12289    }
12290
12291    #[simd_test(enable = "avx512f,avx512vl")]
12292    unsafe fn test_mm256_mask_cvtepi64_storeu_epi8() {
12293        let a = _mm256_set1_epi64x(9);
12294        let mut r = _mm_set1_epi8(0);
12295        _mm256_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12296        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9);
12297        assert_eq_m128i(r, e);
12298    }
12299
12300    #[simd_test(enable = "avx512f,avx512vl")]
12301    unsafe fn test_mm_mask_cvtepi64_storeu_epi8() {
12302        let a = _mm_set1_epi64x(9);
12303        let mut r = _mm_set1_epi8(0);
12304        _mm_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12305        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9);
12306        assert_eq_m128i(r, e);
12307    }
12308
12309    #[simd_test(enable = "avx512f")]
12310    unsafe fn test_mm512_mask_cvtsepi64_storeu_epi8() {
12311        let a = _mm512_set1_epi64(i64::MAX);
12312        let mut r = _mm_set1_epi8(0);
12313        _mm512_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12314        #[rustfmt::skip]
12315        let e = _mm_set_epi8(
12316            0, 0, 0, 0,
12317            0, 0, 0, 0,
12318            i8::MAX, i8::MAX, i8::MAX, i8::MAX,
12319            i8::MAX, i8::MAX, i8::MAX, i8::MAX,
12320        );
12321        assert_eq_m128i(r, e);
12322    }
12323
12324    #[simd_test(enable = "avx512f,avx512vl")]
12325    unsafe fn test_mm256_mask_cvtsepi64_storeu_epi8() {
12326        let a = _mm256_set1_epi64x(i64::MAX);
12327        let mut r = _mm_set1_epi8(0);
12328        _mm256_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12329        #[rustfmt::skip]
12330        let e = _mm_set_epi8(
12331            0, 0, 0, 0,
12332            0, 0, 0, 0,
12333            0, 0, 0, 0,
12334            i8::MAX, i8::MAX, i8::MAX, i8::MAX,
12335        );
12336        assert_eq_m128i(r, e);
12337    }
12338
12339    #[simd_test(enable = "avx512f,avx512vl")]
12340    unsafe fn test_mm_mask_cvtsepi64_storeu_epi8() {
12341        let a = _mm_set1_epi64x(i64::MAX);
12342        let mut r = _mm_set1_epi8(0);
12343        _mm_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12344        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MAX, i8::MAX);
12345        assert_eq_m128i(r, e);
12346    }
12347
12348    #[simd_test(enable = "avx512f")]
12349    unsafe fn test_mm512_mask_cvtusepi64_storeu_epi8() {
12350        let a = _mm512_set1_epi64(i64::MAX);
12351        let mut r = _mm_set1_epi8(0);
12352        _mm512_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12353        #[rustfmt::skip]
12354        let e = _mm_set_epi8(
12355            0, 0, 0, 0,
12356            0, 0, 0, 0,
12357            u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
12358            u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
12359        );
12360        assert_eq_m128i(r, e);
12361    }
12362
12363    #[simd_test(enable = "avx512f,avx512vl")]
12364    unsafe fn test_mm256_mask_cvtusepi64_storeu_epi8() {
12365        let a = _mm256_set1_epi64x(i64::MAX);
12366        let mut r = _mm_set1_epi8(0);
12367        _mm256_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12368        #[rustfmt::skip]
12369        let e = _mm_set_epi8(
12370            0, 0, 0, 0,
12371            0, 0, 0, 0,
12372            0, 0, 0, 0,
12373            u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
12374        );
12375        assert_eq_m128i(r, e);
12376    }
12377
12378    #[simd_test(enable = "avx512f,avx512vl")]
12379    unsafe fn test_mm_mask_cvtusepi64_storeu_epi8() {
12380        let a = _mm_set1_epi64x(i64::MAX);
12381        let mut r = _mm_set1_epi8(0);
12382        _mm_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12383        #[rustfmt::skip]
12384        let e = _mm_set_epi8(
12385            0, 0, 0, 0,
12386            0, 0, 0, 0,
12387            0, 0, 0, 0,
12388            0, 0, u8::MAX as i8, u8::MAX as i8,
12389        );
12390        assert_eq_m128i(r, e);
12391    }
12392
12393    #[simd_test(enable = "avx512f")]
12394    unsafe fn test_mm512_mask_cvtepi64_storeu_epi32() {
12395        let a = _mm512_set1_epi64(9);
12396        let mut r = _mm256_undefined_si256();
12397        _mm512_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
12398        let e = _mm256_set1_epi32(9);
12399        assert_eq_m256i(r, e);
12400    }
12401
12402    #[simd_test(enable = "avx512f,avx512vl")]
12403    unsafe fn test_mm256_mask_cvtepi64_storeu_epi32() {
12404        let a = _mm256_set1_epi64x(9);
12405        let mut r = _mm_set1_epi32(0);
12406        _mm256_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
12407        let e = _mm_set_epi32(9, 9, 9, 9);
12408        assert_eq_m128i(r, e);
12409    }
12410
12411    #[simd_test(enable = "avx512f,avx512vl")]
12412    unsafe fn test_mm_mask_cvtepi64_storeu_epi32() {
12413        let a = _mm_set1_epi64x(9);
12414        let mut r = _mm_set1_epi16(0);
12415        _mm_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
12416        let e = _mm_set_epi32(0, 0, 9, 9);
12417        assert_eq_m128i(r, e);
12418    }
12419
12420    #[simd_test(enable = "avx512f")]
12421    unsafe fn test_mm512_mask_cvtsepi64_storeu_epi32() {
12422        let a = _mm512_set1_epi64(i64::MAX);
12423        let mut r = _mm256_undefined_si256();
12424        _mm512_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
12425        let e = _mm256_set1_epi32(i32::MAX);
12426        assert_eq_m256i(r, e);
12427    }
12428
12429    #[simd_test(enable = "avx512f,avx512vl")]
12430    unsafe fn test_mm256_mask_cvtsepi64_storeu_epi32() {
12431        let a = _mm256_set1_epi64x(i64::MAX);
12432        let mut r = _mm_set1_epi32(0);
12433        _mm256_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a);
12434        let e = _mm_set1_epi32(i32::MAX);
12435        assert_eq_m128i(r, e);
12436    }
12437
12438    #[simd_test(enable = "avx512f,avx512vl")]
12439    unsafe fn test_mm_mask_cvtsepi64_storeu_epi32() {
12440        let a = _mm_set1_epi64x(i64::MAX);
12441        let mut r = _mm_set1_epi16(0);
12442        _mm_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a);
12443        let e = _mm_set_epi32(0, 0, i32::MAX, i32::MAX);
12444        assert_eq_m128i(r, e);
12445    }
12446
12447    #[simd_test(enable = "avx512f")]
12448    unsafe fn test_mm512_mask_cvtusepi64_storeu_epi32() {
12449        let a = _mm512_set1_epi64(i64::MAX);
12450        let mut r = _mm256_undefined_si256();
12451        _mm512_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
12452        let e = _mm256_set1_epi32(u32::MAX as i32);
12453        assert_eq_m256i(r, e);
12454    }
12455
12456    #[simd_test(enable = "avx512f,avx512vl")]
12457    unsafe fn test_mm256_mask_cvtusepi64_storeu_epi32() {
12458        let a = _mm256_set1_epi64x(i64::MAX);
12459        let mut r = _mm_set1_epi32(0);
12460        _mm256_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a);
12461        let e = _mm_set1_epi32(u32::MAX as i32);
12462        assert_eq_m128i(r, e);
12463    }
12464
12465    #[simd_test(enable = "avx512f,avx512vl")]
12466    unsafe fn test_mm_mask_cvtusepi64_storeu_epi32() {
12467        let a = _mm_set1_epi64x(i64::MAX);
12468        let mut r = _mm_set1_epi16(0);
12469        _mm_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a);
12470        let e = _mm_set_epi32(0, 0, u32::MAX as i32, u32::MAX as i32);
12471        assert_eq_m128i(r, e);
12472    }
12473
12474    #[simd_test(enable = "avx512f")]
12475    unsafe fn test_mm512_storeu_epi64() {
12476        let a = _mm512_set1_epi64(9);
12477        let mut r = _mm512_set1_epi64(0);
12478        _mm512_storeu_epi64(&mut r as *mut _ as *mut i64, a);
12479        assert_eq_m512i(r, a);
12480    }
12481
12482    #[simd_test(enable = "avx512f,avx512vl")]
12483    unsafe fn test_mm256_storeu_epi64() {
12484        let a = _mm256_set1_epi64x(9);
12485        let mut r = _mm256_set1_epi64x(0);
12486        _mm256_storeu_epi64(&mut r as *mut _ as *mut i64, a);
12487        assert_eq_m256i(r, a);
12488    }
12489
12490    #[simd_test(enable = "avx512f,avx512vl")]
12491    unsafe fn test_mm_storeu_epi64() {
12492        let a = _mm_set1_epi64x(9);
12493        let mut r = _mm_set1_epi64x(0);
12494        _mm_storeu_epi64(&mut r as *mut _ as *mut i64, a);
12495        assert_eq_m128i(r, a);
12496    }
12497
12498    #[simd_test(enable = "avx512f")]
12499    unsafe fn test_mm512_load_epi64() {
12500        #[repr(align(64))]
12501        struct Align {
12502            data: [i64; 8], // 64 bytes
12503        }
12504        let a = Align {
12505            data: [4, 3, 2, 5, -8, -9, -64, -50],
12506        };
12507        let p = (a.data).as_ptr();
12508        let r = _mm512_load_epi64(black_box(p));
12509        let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50);
12510        assert_eq_m512i(r, e);
12511    }
12512
12513    #[simd_test(enable = "avx512f,avx512vl")]
12514    unsafe fn test_mm256_load_epi64() {
12515        #[repr(align(64))]
12516        struct Align {
12517            data: [i64; 4],
12518        }
12519        let a = Align { data: [4, 3, 2, 5] };
12520        let p = (a.data).as_ptr();
12521        let r = _mm256_load_epi64(black_box(p));
12522        let e = _mm256_set_epi64x(5, 2, 3, 4);
12523        assert_eq_m256i(r, e);
12524    }
12525
12526    #[simd_test(enable = "avx512f,avx512vl")]
12527    unsafe fn test_mm_load_epi64() {
12528        #[repr(align(64))]
12529        struct Align {
12530            data: [i64; 2],
12531        }
12532        let a = Align { data: [4, 3] };
12533        let p = (a.data).as_ptr();
12534        let r = _mm_load_epi64(black_box(p));
12535        let e = _mm_set_epi64x(3, 4);
12536        assert_eq_m128i(r, e);
12537    }
12538
12539    #[simd_test(enable = "avx512f")]
12540    unsafe fn test_mm512_store_epi64() {
12541        let a = _mm512_set1_epi64(9);
12542        let mut r = _mm512_set1_epi64(0);
12543        _mm512_store_epi64(&mut r as *mut _ as *mut i64, a);
12544        assert_eq_m512i(r, a);
12545    }
12546
12547    #[simd_test(enable = "avx512f,avx512vl")]
12548    unsafe fn test_mm256_store_epi64() {
12549        let a = _mm256_set1_epi64x(9);
12550        let mut r = _mm256_set1_epi64x(0);
12551        _mm256_store_epi64(&mut r as *mut _ as *mut i64, a);
12552        assert_eq_m256i(r, a);
12553    }
12554
12555    #[simd_test(enable = "avx512f,avx512vl")]
12556    unsafe fn test_mm_store_epi64() {
12557        let a = _mm_set1_epi64x(9);
12558        let mut r = _mm_set1_epi64x(0);
12559        _mm_store_epi64(&mut r as *mut _ as *mut i64, a);
12560        assert_eq_m128i(r, a);
12561    }
12562
12563    #[simd_test(enable = "avx512f")]
12564    unsafe fn test_mm512_load_pd() {
12565        #[repr(align(64))]
12566        struct Align {
12567            data: [f64; 8], // 64 bytes
12568        }
12569        let a = Align {
12570            data: [4., 3., 2., 5., -8., -9., -64., -50.],
12571        };
12572        let p = (a.data).as_ptr();
12573        let r = _mm512_load_pd(black_box(p));
12574        let e = _mm512_setr_pd(4., 3., 2., 5., -8., -9., -64., -50.);
12575        assert_eq_m512d(r, e);
12576    }
12577
12578    #[simd_test(enable = "avx512f")]
12579    unsafe fn test_mm512_store_pd() {
12580        let a = _mm512_set1_pd(9.);
12581        let mut r = _mm512_undefined_pd();
12582        _mm512_store_pd(&mut r as *mut _ as *mut f64, a);
12583        assert_eq_m512d(r, a);
12584    }
12585
12586    #[simd_test(enable = "avx512f")]
12587    unsafe fn test_mm512_test_epi64_mask() {
12588        let a = _mm512_set1_epi64(1 << 0);
12589        let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
12590        let r = _mm512_test_epi64_mask(a, b);
12591        let e: __mmask8 = 0b11111111;
12592        assert_eq!(r, e);
12593    }
12594
12595    #[simd_test(enable = "avx512f")]
12596    unsafe fn test_mm512_mask_test_epi64_mask() {
12597        let a = _mm512_set1_epi64(1 << 0);
12598        let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
12599        let r = _mm512_mask_test_epi64_mask(0, a, b);
12600        assert_eq!(r, 0);
12601        let r = _mm512_mask_test_epi64_mask(0b11111111, a, b);
12602        let e: __mmask8 = 0b11111111;
12603        assert_eq!(r, e);
12604    }
12605
12606    #[simd_test(enable = "avx512f,avx512vl")]
12607    unsafe fn test_mm256_test_epi64_mask() {
12608        let a = _mm256_set1_epi64x(1 << 0);
12609        let b = _mm256_set1_epi64x(1 << 0 | 1 << 1);
12610        let r = _mm256_test_epi64_mask(a, b);
12611        let e: __mmask8 = 0b00001111;
12612        assert_eq!(r, e);
12613    }
12614
12615    #[simd_test(enable = "avx512f,avx512vl")]
12616    unsafe fn test_mm256_mask_test_epi64_mask() {
12617        let a = _mm256_set1_epi64x(1 << 0);
12618        let b = _mm256_set1_epi64x(1 << 0 | 1 << 1);
12619        let r = _mm256_mask_test_epi64_mask(0, a, b);
12620        assert_eq!(r, 0);
12621        let r = _mm256_mask_test_epi64_mask(0b00001111, a, b);
12622        let e: __mmask8 = 0b00001111;
12623        assert_eq!(r, e);
12624    }
12625
12626    #[simd_test(enable = "avx512f,avx512vl")]
12627    unsafe fn test_mm_test_epi64_mask() {
12628        let a = _mm_set1_epi64x(1 << 0);
12629        let b = _mm_set1_epi64x(1 << 0 | 1 << 1);
12630        let r = _mm_test_epi64_mask(a, b);
12631        let e: __mmask8 = 0b00000011;
12632        assert_eq!(r, e);
12633    }
12634
12635    #[simd_test(enable = "avx512f,avx512vl")]
12636    unsafe fn test_mm_mask_test_epi64_mask() {
12637        let a = _mm_set1_epi64x(1 << 0);
12638        let b = _mm_set1_epi64x(1 << 0 | 1 << 1);
12639        let r = _mm_mask_test_epi64_mask(0, a, b);
12640        assert_eq!(r, 0);
12641        let r = _mm_mask_test_epi64_mask(0b00000011, a, b);
12642        let e: __mmask8 = 0b00000011;
12643        assert_eq!(r, e);
12644    }
12645
12646    #[simd_test(enable = "avx512f")]
12647    unsafe fn test_mm512_testn_epi64_mask() {
12648        let a = _mm512_set1_epi64(1 << 0);
12649        let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
12650        let r = _mm512_testn_epi64_mask(a, b);
12651        let e: __mmask8 = 0b00000000;
12652        assert_eq!(r, e);
12653    }
12654
12655    #[simd_test(enable = "avx512f")]
12656    unsafe fn test_mm512_mask_testn_epi64_mask() {
12657        let a = _mm512_set1_epi64(1 << 0);
12658        let b = _mm512_set1_epi64(1 << 1);
12659        let r = _mm512_mask_testn_epi64_mask(0, a, b);
12660        assert_eq!(r, 0);
12661        let r = _mm512_mask_testn_epi64_mask(0b11111111, a, b);
12662        let e: __mmask8 = 0b11111111;
12663        assert_eq!(r, e);
12664    }
12665
12666    #[simd_test(enable = "avx512f,avx512vl")]
12667    unsafe fn test_mm256_testn_epi64_mask() {
12668        let a = _mm256_set1_epi64x(1 << 0);
12669        let b = _mm256_set1_epi64x(1 << 1);
12670        let r = _mm256_testn_epi64_mask(a, b);
12671        let e: __mmask8 = 0b00001111;
12672        assert_eq!(r, e);
12673    }
12674
12675    #[simd_test(enable = "avx512f,avx512vl")]
12676    unsafe fn test_mm256_mask_testn_epi64_mask() {
12677        let a = _mm256_set1_epi64x(1 << 0);
12678        let b = _mm256_set1_epi64x(1 << 1);
12679        let r = _mm256_mask_testn_epi64_mask(0, a, b);
12680        assert_eq!(r, 0);
12681        let r = _mm256_mask_testn_epi64_mask(0b11111111, a, b);
12682        let e: __mmask8 = 0b00001111;
12683        assert_eq!(r, e);
12684    }
12685
12686    #[simd_test(enable = "avx512f,avx512vl")]
12687    unsafe fn test_mm_testn_epi64_mask() {
12688        let a = _mm_set1_epi64x(1 << 0);
12689        let b = _mm_set1_epi64x(1 << 1);
12690        let r = _mm_testn_epi64_mask(a, b);
12691        let e: __mmask8 = 0b00000011;
12692        assert_eq!(r, e);
12693    }
12694
12695    #[simd_test(enable = "avx512f,avx512vl")]
12696    unsafe fn test_mm_mask_testn_epi64_mask() {
12697        let a = _mm_set1_epi64x(1 << 0);
12698        let b = _mm_set1_epi64x(1 << 1);
12699        let r = _mm_mask_testn_epi64_mask(0, a, b);
12700        assert_eq!(r, 0);
12701        let r = _mm_mask_testn_epi64_mask(0b11111111, a, b);
12702        let e: __mmask8 = 0b00000011;
12703        assert_eq!(r, e);
12704    }
12705
12706    #[simd_test(enable = "avx512f")]
12707    unsafe fn test_mm512_mask_set1_epi64() {
12708        let src = _mm512_set1_epi64(2);
12709        let a: i64 = 11;
12710        let r = _mm512_mask_set1_epi64(src, 0, a);
12711        assert_eq_m512i(r, src);
12712        let r = _mm512_mask_set1_epi64(src, 0b11111111, a);
12713        let e = _mm512_set1_epi64(11);
12714        assert_eq_m512i(r, e);
12715    }
12716
12717    #[simd_test(enable = "avx512f")]
12718    unsafe fn test_mm512_maskz_set1_epi64() {
12719        let a: i64 = 11;
12720        let r = _mm512_maskz_set1_epi64(0, a);
12721        assert_eq_m512i(r, _mm512_setzero_si512());
12722        let r = _mm512_maskz_set1_epi64(0b11111111, a);
12723        let e = _mm512_set1_epi64(11);
12724        assert_eq_m512i(r, e);
12725    }
12726
12727    #[simd_test(enable = "avx512f,avx512vl")]
12728    unsafe fn test_mm256_mask_set1_epi64() {
12729        let src = _mm256_set1_epi64x(2);
12730        let a: i64 = 11;
12731        let r = _mm256_mask_set1_epi64(src, 0, a);
12732        assert_eq_m256i(r, src);
12733        let r = _mm256_mask_set1_epi64(src, 0b00001111, a);
12734        let e = _mm256_set1_epi64x(11);
12735        assert_eq_m256i(r, e);
12736    }
12737
12738    #[simd_test(enable = "avx512f,avx512vl")]
12739    unsafe fn test_mm256_maskz_set1_epi64() {
12740        let a: i64 = 11;
12741        let r = _mm256_maskz_set1_epi64(0, a);
12742        assert_eq_m256i(r, _mm256_setzero_si256());
12743        let r = _mm256_maskz_set1_epi64(0b00001111, a);
12744        let e = _mm256_set1_epi64x(11);
12745        assert_eq_m256i(r, e);
12746    }
12747
12748    #[simd_test(enable = "avx512f,avx512vl")]
12749    unsafe fn test_mm_mask_set1_epi64() {
12750        let src = _mm_set1_epi64x(2);
12751        let a: i64 = 11;
12752        let r = _mm_mask_set1_epi64(src, 0, a);
12753        assert_eq_m128i(r, src);
12754        let r = _mm_mask_set1_epi64(src, 0b00000011, a);
12755        let e = _mm_set1_epi64x(11);
12756        assert_eq_m128i(r, e);
12757    }
12758
12759    #[simd_test(enable = "avx512f,avx512vl")]
12760    unsafe fn test_mm_maskz_set1_epi64() {
12761        let a: i64 = 11;
12762        let r = _mm_maskz_set1_epi64(0, a);
12763        assert_eq_m128i(r, _mm_setzero_si128());
12764        let r = _mm_maskz_set1_epi64(0b00000011, a);
12765        let e = _mm_set1_epi64x(11);
12766        assert_eq_m128i(r, e);
12767    }
12768
12769    #[simd_test(enable = "avx512f")]
12770    unsafe fn test_mm_cvtsd_i64() {
12771        let a = _mm_set_pd(1., -1.5);
12772        let r = _mm_cvtsd_i64(a);
12773        let e: i64 = -2;
12774        assert_eq!(r, e);
12775    }
12776
12777    #[simd_test(enable = "avx512f")]
12778    unsafe fn test_mm_cvtss_i64() {
12779        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12780        let r = _mm_cvtss_i64(a);
12781        let e: i64 = -2;
12782        assert_eq!(r, e);
12783    }
12784
12785    #[simd_test(enable = "avx512f")]
12786    unsafe fn test_mm_cvt_roundi64_ss() {
12787        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12788        let b: i64 = 9;
12789        let r = _mm_cvt_roundi64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12790        let e = _mm_set_ps(0., -0.5, 1., 9.);
12791        assert_eq_m128(r, e);
12792    }
12793
12794    #[simd_test(enable = "avx512f")]
12795    unsafe fn test_mm_cvt_roundsi64_ss() {
12796        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12797        let b: i64 = 9;
12798        let r = _mm_cvt_roundsi64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12799        let e = _mm_set_ps(0., -0.5, 1., 9.);
12800        assert_eq_m128(r, e);
12801    }
12802
12803    #[simd_test(enable = "avx512f")]
12804    unsafe fn test_mm_cvti64_ss() {
12805        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12806        let b: i64 = 9;
12807        let r = _mm_cvti64_ss(a, b);
12808        let e = _mm_set_ps(0., -0.5, 1., 9.);
12809        assert_eq_m128(r, e);
12810    }
12811
12812    #[simd_test(enable = "avx512f")]
12813    unsafe fn test_mm_cvti64_sd() {
12814        let a = _mm_set_pd(1., -1.5);
12815        let b: i64 = 9;
12816        let r = _mm_cvti64_sd(a, b);
12817        let e = _mm_set_pd(1., 9.);
12818        assert_eq_m128d(r, e);
12819    }
12820
12821    #[simd_test(enable = "avx512f")]
12822    unsafe fn test_mm_cvt_roundsd_si64() {
12823        let a = _mm_set_pd(1., -1.5);
12824        let r = _mm_cvt_roundsd_si64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12825        let e: i64 = -1;
12826        assert_eq!(r, e);
12827    }
12828
12829    #[simd_test(enable = "avx512f")]
12830    unsafe fn test_mm_cvt_roundsd_i64() {
12831        let a = _mm_set_pd(1., -1.5);
12832        let r = _mm_cvt_roundsd_i64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12833        let e: i64 = -1;
12834        assert_eq!(r, e);
12835    }
12836
12837    #[simd_test(enable = "avx512f")]
12838    unsafe fn test_mm_cvt_roundsd_u64() {
12839        let a = _mm_set_pd(1., f64::MAX);
12840        let r = _mm_cvt_roundsd_u64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12841        let e: u64 = u64::MAX;
12842        assert_eq!(r, e);
12843    }
12844
12845    #[simd_test(enable = "avx512f")]
12846    unsafe fn test_mm_cvtsd_u64() {
12847        let a = _mm_set_pd(1., -1.5);
12848        let r = _mm_cvtsd_u64(a);
12849        let e: u64 = u64::MAX;
12850        assert_eq!(r, e);
12851    }
12852
12853    #[simd_test(enable = "avx512f")]
12854    unsafe fn test_mm_cvt_roundss_i64() {
12855        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12856        let r = _mm_cvt_roundss_i64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12857        let e: i64 = -1;
12858        assert_eq!(r, e);
12859    }
12860
12861    #[simd_test(enable = "avx512f")]
12862    unsafe fn test_mm_cvt_roundss_si64() {
12863        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12864        let r = _mm_cvt_roundss_si64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12865        let e: i64 = -1;
12866        assert_eq!(r, e);
12867    }
12868
12869    #[simd_test(enable = "avx512f")]
12870    unsafe fn test_mm_cvt_roundss_u64() {
12871        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12872        let r = _mm_cvt_roundss_u64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12873        let e: u64 = u64::MAX;
12874        assert_eq!(r, e);
12875    }
12876
12877    #[simd_test(enable = "avx512f")]
12878    unsafe fn test_mm_cvtss_u64() {
12879        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12880        let r = _mm_cvtss_u64(a);
12881        let e: u64 = u64::MAX;
12882        assert_eq!(r, e);
12883    }
12884
12885    #[simd_test(enable = "avx512f")]
12886    unsafe fn test_mm_cvttsd_i64() {
12887        let a = _mm_set_pd(1., -1.5);
12888        let r = _mm_cvttsd_i64(a);
12889        let e: i64 = -1;
12890        assert_eq!(r, e);
12891    }
12892
12893    #[simd_test(enable = "avx512f")]
12894    unsafe fn test_mm_cvtt_roundsd_i64() {
12895        let a = _mm_set_pd(1., -1.5);
12896        let r = _mm_cvtt_roundsd_i64::<_MM_FROUND_NO_EXC>(a);
12897        let e: i64 = -1;
12898        assert_eq!(r, e);
12899    }
12900
12901    #[simd_test(enable = "avx512f")]
12902    unsafe fn test_mm_cvtt_roundsd_si64() {
12903        let a = _mm_set_pd(1., -1.5);
12904        let r = _mm_cvtt_roundsd_si64::<_MM_FROUND_NO_EXC>(a);
12905        let e: i64 = -1;
12906        assert_eq!(r, e);
12907    }
12908
12909    #[simd_test(enable = "avx512f")]
12910    unsafe fn test_mm_cvtt_roundsd_u64() {
12911        let a = _mm_set_pd(1., -1.5);
12912        let r = _mm_cvtt_roundsd_u64::<_MM_FROUND_NO_EXC>(a);
12913        let e: u64 = u64::MAX;
12914        assert_eq!(r, e);
12915    }
12916
12917    #[simd_test(enable = "avx512f")]
12918    unsafe fn test_mm_cvttsd_u64() {
12919        let a = _mm_set_pd(1., -1.5);
12920        let r = _mm_cvttsd_u64(a);
12921        let e: u64 = u64::MAX;
12922        assert_eq!(r, e);
12923    }
12924
12925    #[simd_test(enable = "avx512f")]
12926    unsafe fn test_mm_cvttss_i64() {
12927        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12928        let r = _mm_cvttss_i64(a);
12929        let e: i64 = -1;
12930        assert_eq!(r, e);
12931    }
12932
12933    #[simd_test(enable = "avx512f")]
12934    unsafe fn test_mm_cvtt_roundss_i64() {
12935        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12936        let r = _mm_cvtt_roundss_i64::<_MM_FROUND_NO_EXC>(a);
12937        let e: i64 = -1;
12938        assert_eq!(r, e);
12939    }
12940
12941    #[simd_test(enable = "avx512f")]
12942    unsafe fn test_mm_cvtt_roundss_si64() {
12943        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12944        let r = _mm_cvtt_roundss_si64::<_MM_FROUND_NO_EXC>(a);
12945        let e: i64 = -1;
12946        assert_eq!(r, e);
12947    }
12948
12949    #[simd_test(enable = "avx512f")]
12950    unsafe fn test_mm_cvtt_roundss_u64() {
12951        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12952        let r = _mm_cvtt_roundss_u64::<_MM_FROUND_NO_EXC>(a);
12953        let e: u64 = u64::MAX;
12954        assert_eq!(r, e);
12955    }
12956
12957    #[simd_test(enable = "avx512f")]
12958    unsafe fn test_mm_cvttss_u64() {
12959        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12960        let r = _mm_cvttss_u64(a);
12961        let e: u64 = u64::MAX;
12962        assert_eq!(r, e);
12963    }
12964
12965    #[simd_test(enable = "avx512f")]
12966    unsafe fn test_mm_cvtu64_ss() {
12967        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12968        let b: u64 = 9;
12969        let r = _mm_cvtu64_ss(a, b);
12970        let e = _mm_set_ps(0., -0.5, 1., 9.);
12971        assert_eq_m128(r, e);
12972    }
12973
12974    #[simd_test(enable = "avx512f")]
12975    unsafe fn test_mm_cvtu64_sd() {
12976        let a = _mm_set_pd(1., -1.5);
12977        let b: u64 = 9;
12978        let r = _mm_cvtu64_sd(a, b);
12979        let e = _mm_set_pd(1., 9.);
12980        assert_eq_m128d(r, e);
12981    }
12982
12983    #[simd_test(enable = "avx512f")]
12984    unsafe fn test_mm_cvt_roundu64_ss() {
12985        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12986        let b: u64 = 9;
12987        let r = _mm_cvt_roundu64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12988        let e = _mm_set_ps(0., -0.5, 1., 9.);
12989        assert_eq_m128(r, e);
12990    }
12991
12992    #[simd_test(enable = "avx512f")]
12993    unsafe fn test_mm_cvt_roundu64_sd() {
12994        let a = _mm_set_pd(1., -1.5);
12995        let b: u64 = 9;
12996        let r = _mm_cvt_roundu64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12997        let e = _mm_set_pd(1., 9.);
12998        assert_eq_m128d(r, e);
12999    }
13000
13001    #[simd_test(enable = "avx512f")]
13002    unsafe fn test_mm_cvt_roundi64_sd() {
13003        let a = _mm_set_pd(1., -1.5);
13004        let b: i64 = 9;
13005        let r = _mm_cvt_roundi64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
13006        let e = _mm_set_pd(1., 9.);
13007        assert_eq_m128d(r, e);
13008    }
13009
13010    #[simd_test(enable = "avx512f")]
13011    unsafe fn test_mm_cvt_roundsi64_sd() {
13012        let a = _mm_set_pd(1., -1.5);
13013        let b: i64 = 9;
13014        let r = _mm_cvt_roundsi64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
13015        let e = _mm_set_pd(1., 9.);
13016        assert_eq_m128d(r, e);
13017    }
13018}